Texas Instruments TMS320DM643X DMP manual Uart Block Diagram, Fifo

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Introduction

Peripheral Bus

Figure 1. UART Block Diagram

S
e		8			8
l		8	Receiver		8
e	8		FIFO
c	8
c
t
			8				Receiver	RX
Data	Receiver		8				Shift	RX
Data	Receiver						Shift	pin
Bus	Buffer						Register	pin
Buffer	Register
16
	Line						Receiver
	Line						Timing and
	Control						Timing and
	Control						Control
	Register						Control
	Register
	Divisor
	Latch (LS)	16	Baud
		16	Baud
	Divisor		Generator
	Divisor
	Latch (MS)
	Line						Transmitter
	Line						Timing and
	Status						Timing and
	Status						Control
	Register						Control
	Register
	8		Transmitter	8	S
			FIFO		e
					l
	Transmitter		8		e	8	Transmitter	TX
	Holding				c		Shift	pin
	Register				t		Register	pin
	Register				t		Register
	Modem	8					Control
	Control	8					Control
	Control						Logic
	Register						Logic
	Register
	Interrupt	8	Interrupt/
	Enable	8	Event
	Enable		Event			Interrupt to CPU
	Register		Control			Interrupt to CPU
	Register		Control
			Logic			Event to DMA controller
						Event to DMA controller
	Interrupt	8
	Identification	8
	Identification						Power and
	Register						Power and
							Emulation
							Control
	FIFO						Register
	Control
	Register

SPRU997C –December 2009	Universal Asynchronous Receiver/Transmitter (UART)	9
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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesUart Supported Features/Characteristics by Instance Functional Block DiagramFeature Support Industry Standards Compliance StatementFifo Uart Block DiagramUart Clock Generation and ControlDlhdll BclkBaud Rate Divisor Value Actual Baud Rate Error % Baud Rate Examples for 27 MHz Uart Input ClockStart Parity STOP1 STOP2 Signal Descriptions Pin MultiplexingProtocol Description Data Format Endianness ConsiderationsParity STOP1 ParityOperation Fifo Modes Character Time for Word LengthsCharacter Time Four Character Times Autoflow Control Uart Interface Using Autoflow DiagramLoopback Control Autoflow Functional Timing Waveforms for RTSReset Considerations InitializationInterrupt Support Uart Interrupt Requests Descriptions Enable bitsUart Interrupt Request Interrupt Source CommentPower Management DMA Event SupportEmulation Considerations Exception Processing Changing Operating Mode During Busy Serial CommunicationDivisor Latch Not Programmed Uart RegistersReceiver Buffer Register RBR Access considerationsReceiver Buffer Register RBR Field Descriptions Bit FieldTransmitter Holding Register THR Transmitter Holding Register THR Field DescriptionsBit Field Value Description Interrupt Enable Register IER Field Descriptions Interrupt Enable Register IERElsi Etbei Erbi ElsiAccess consideration Interrupt Identification Register IIRInterrupt Identification Register IIR Field Descriptions Interrupt Identification and Interrupt Clearing Information Fifo Control Register FCRIIR Bits Interrupt Type Interrupt SourceRxfiftl Fifo Control Register FCR Field DescriptionsDMAMODE11 Txclr Rxclr Fifoen DMAMODE1Line Control Register LCR Field Descriptions Line Control Register LCRDlab EPS PEN STB WLS DlabNumber of Stop Bits Generated Relationship Between ST, EPS, and PEN Bits in LCRST Bit EPS Bit PEN Bit Parity Option STB BitModem Control Register MCR Field Descriptions Modem Control Register MCRLoop AFEFifo mode Non-FIFO modeLine Status Register LSR Line Status Register LSR Field DescriptionsSet Elsi = 1 in IER, an interrupt request is generated Register RBR Divisor Latches DLL and DLHDivisor MSB Latch DLH Field Descriptions Divisor LSB Latch DLL Field DescriptionsCLS REV Peripheral Identification Registers PID1 and PID2CLS TYPUtrst Urrst Power and Emulation Management Register PwremumgmtFree UtrstReference Additions/Modifications/Deletions Document Revision HistoryImportant Notice

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