Texas Instruments TMS320DM643X DMP manual Revision History, Appendix a

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Preface			6
1	Introduction		7
	1.1	Purpose of the Peripheral	7
	1.2	Features	7
	1.3	Functional Block Diagram	8
	1.4	Industry Standard(s) Compliance Statement	8
2	Peripheral Architecture		10
	2.1	Clock Generation and Control	10
	2.2	Signal Descriptions	12
	2.3	Pin Multiplexing	12
	2.4	Protocol Description	12
	2.5	Endianness Considerations	13
	2.6	Operation	14
	2.7	Reset Considerations	18
	2.8	Initialization	18
	2.9	Interrupt Support	18
	2.10	DMA Event Support	20
	2.11	Power Management	20
	2.12	Emulation Considerations	20
	2.13	Exception Processing	21
3	Registers		21
	3.1	Receiver Buffer Register (RBR)	22
	3.2	Transmitter Holding Register (THR)	23
	3.3	Interrupt Enable Register (IER)	24
	3.4	Interrupt Identification Register (IIR)	25
	3.5	FIFO Control Register (FCR)	26
	3.6	Line Control Register (LCR)	28
	3.7	Modem Control Register (MCR)	30
	3.8	Line Status Register (LSR)	31
	3.9	Divisor Latches (DLL and DLH)	33
	3.10	Peripheral Identification Registers (PID1 and PID2)	35
	3.11	Power and Emulation Management Register (PWREMU_MGMT)	36
Appendix A		Revision History	37

SPRU997C –December 2009	Table of Contents	3
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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramUart Supported Features/Characteristics by Instance Feature SupportFifo Uart Block DiagramBclk Clock Generation and ControlUart DlhdllBaud Rate Divisor Value Actual Baud Rate Error % Baud Rate Examples for 27 MHz Uart Input ClockStart Parity STOP1 STOP2 Signal Descriptions Pin MultiplexingProtocol Description Parity Endianness ConsiderationsData Format Parity STOP1Operation Fifo Modes Character Time for Word LengthsCharacter Time Four Character Times Autoflow Control Uart Interface Using Autoflow DiagramLoopback Control Autoflow Functional Timing Waveforms for RTSReset Considerations InitializationInterrupt Support Comment Enable bitsUart Interrupt Requests Descriptions Uart Interrupt Request Interrupt SourcePower Management DMA Event SupportEmulation Considerations Uart Registers Changing Operating Mode During Busy Serial CommunicationException Processing Divisor Latch Not ProgrammedBit Field Access considerationsReceiver Buffer Register RBR Receiver Buffer Register RBR Field DescriptionsTransmitter Holding Register THR Transmitter Holding Register THR Field DescriptionsBit Field Value Description Elsi Interrupt Enable Register IERInterrupt Enable Register IER Field Descriptions Elsi Etbei ErbiAccess consideration Interrupt Identification Register IIRInterrupt Identification Register IIR Field Descriptions Interrupt Type Interrupt Source Fifo Control Register FCRInterrupt Identification and Interrupt Clearing Information IIR BitsDMAMODE1 Fifo Control Register FCR Field DescriptionsRxfiftl DMAMODE11 Txclr Rxclr FifoenDlab Line Control Register LCRLine Control Register LCR Field Descriptions Dlab EPS PEN STB WLSSTB Bit Relationship Between ST, EPS, and PEN Bits in LCRNumber of Stop Bits Generated ST Bit EPS Bit PEN Bit Parity OptionAFE Modem Control Register MCRModem Control Register MCR Field Descriptions LoopLine Status Register LSR Field Descriptions Non-FIFO modeFifo mode Line Status Register LSRSet Elsi = 1 in IER, an interrupt request is generated Register RBR Divisor Latches DLL and DLHDivisor MSB Latch DLH Field Descriptions Divisor LSB Latch DLL Field DescriptionsTYP Peripheral Identification Registers PID1 and PID2CLS REV CLSUtrst Power and Emulation Management Register PwremumgmtUtrst Urrst FreeReference Additions/Modifications/Deletions Document Revision HistoryImportant Notice

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