Texas Instruments TMS320DM643X DMP manual Exception Processing, Divisor Latch Not Programmed

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Registers

2.13 Exception Processing

2.13.1Divisor Latch Not Programmed

Since the processor reset signal has no effect on the divisor latch, the divisor latch will have an unknown value after power up. If the divisor latch is not programmed after power up, the baud clock (BCLK) will not operate and will instead be set to a constant logic 1 state.

The divisor latch values should always be reinitialized following a processor reset.

2.13.2Changing Operating Mode During Busy Serial Communication

Since the serial link characteristics are based on how the control registers are programmed, the UART will expect the control registers to be static while it is busy engaging in a serial communication. Therefore, changing the control registers while the module is still busy communicating with another serial device will most likely cause an error condition and should be avoided.

3Registers

The system programmer has access to and control over any of the UART registers that are listed in Table 6. These registers, which control UART operations, receive data, and transmit data, are available at 32-bit addresses in the device memory map. See the device-specific data manual for the memory address of these registers.

•RBR, THR, and DLL share one address. When the DLAB bit in LCR is 0, reading from the address gives the content of RBR, and writing to the address modifies THR. When DLAB = 1, all accesses at the address read or modify DLL. DLL can also be accessed with address offset 20h.

•IER and DLH share one address. When DLAB = 0, all accesses read or modify IER. When DLAB = 1, all accesses read or modify DLH. DLH can also be accessed with address offset 24h.

•IIR and FCR share one address. Regardless of the value of the DLAB bit, reading from the address gives the content of IIR, and writing modifies FCR.

Table 6. UART Registers

Offset

Acronym

Register Description

Section

0h

RBR

Receiver Buffer Register (read only)

Section 3.1

0h

THR

Transmitter Holding Register (write only)

Section 3.2

4h

IER

Interrupt Enable Register

Section 3.3

8h

IIR

Interrupt Identification Register (read only)

Section 3.4

8h

FCR

FIFO Control Register (write only)

Section 3.5

Ch

LCR

Line Control Register

Section 3.6

10h

MCR

Modem Control Register

Section 3.7

14h

LSR

Line Status Register

Section 3.8

20h

DLL

Divisor LSB Latch

Section 3.9

24h

DLH

Divisor MSB Latch

Section 3.9

28h

PID1

Peripheral Identification Register 1

Section 3.10

2Ch

PID2

Peripheral Identification Register 2

Section 3.10

30h

PWREMU_MGMT

Power and Emulation Management Register

Section 3.11

 

 

 

 

SPRU997C –December 2009

Universal Asynchronous Receiver/Transmitter (UART)

21

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Copyright © 2009, Texas Instruments Incorporated

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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesUart Supported Features/Characteristics by Instance Functional Block DiagramFeature Support Industry Standards Compliance StatementFifo Uart Block DiagramUart Clock Generation and ControlDlhdll BclkBaud Rate Divisor Value Actual Baud Rate Error % Baud Rate Examples for 27 MHz Uart Input ClockStart Parity STOP1 STOP2 Signal Descriptions Pin MultiplexingProtocol Description Data Format Endianness ConsiderationsParity STOP1 ParityOperation Fifo Modes Character Time for Word LengthsCharacter Time Four Character Times Autoflow Control Uart Interface Using Autoflow DiagramLoopback Control Autoflow Functional Timing Waveforms for RTSReset Considerations InitializationInterrupt Support Uart Interrupt Requests Descriptions Enable bitsUart Interrupt Request Interrupt Source CommentPower Management DMA Event SupportEmulation Considerations Exception Processing Changing Operating Mode During Busy Serial CommunicationDivisor Latch Not Programmed Uart RegistersReceiver Buffer Register RBR Access considerationsReceiver Buffer Register RBR Field Descriptions Bit FieldTransmitter Holding Register THR Transmitter Holding Register THR Field DescriptionsBit Field Value Description Interrupt Enable Register IER Field Descriptions Interrupt Enable Register IERElsi Etbei Erbi ElsiAccess consideration Interrupt Identification Register IIRInterrupt Identification Register IIR Field Descriptions Interrupt Identification and Interrupt Clearing Information Fifo Control Register FCRIIR Bits Interrupt Type Interrupt SourceRxfiftl Fifo Control Register FCR Field DescriptionsDMAMODE11 Txclr Rxclr Fifoen DMAMODE1Line Control Register LCR Field Descriptions Line Control Register LCRDlab EPS PEN STB WLS DlabNumber of Stop Bits Generated Relationship Between ST, EPS, and PEN Bits in LCRST Bit EPS Bit PEN Bit Parity Option STB BitModem Control Register MCR Field Descriptions Modem Control Register MCRLoop AFEFifo mode Non-FIFO modeLine Status Register LSR Line Status Register LSR Field DescriptionsSet Elsi = 1 in IER, an interrupt request is generated Register RBR Divisor Latches DLL and DLHDivisor MSB Latch DLH Field Descriptions Divisor LSB Latch DLL Field DescriptionsCLS REV Peripheral Identification Registers PID1 and PID2CLS TYPUtrst Urrst Power and Emulation Management Register PwremumgmtFree UtrstReference Additions/Modifications/Deletions Document Revision HistoryImportant Notice
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