Texas Instruments TMS320DM643X DMP manual Interrupt Enable Register IER, Elsi Etbei Erbi

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Registers

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3.3Interrupt Enable Register (IER)

The interrupt enable register (IER) is used to individually enable or disable each type of interrupt request that can be generated by the UART. Each interrupt request that is enabled in IER is forwarded to the CPU. IER is shown in Figure 11 and described in Table 9.

Access considerations:

IER and DLH share one address. To read or modify IER, write 0 to the DLAB bit in LCR. When DLAB = 1, all accesses at the shared address read or modify DLH.

DLH also has a dedicated address. If you use the dedicated address, you can keep DLAB = 0, so that IER is always selected at the shared address.

Figure 11. Interrupt Enable Register (IER)

31					16
Reserved

R-0
15	4	3	2	1	0

Reserved		Rsvd	ELSI	ETBEI	ERBI

R-0		R/W-0	R/W-0	R/W-0	R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

			Table 9. Interrupt Enable Register (IER) Field Descriptions

Bit	Field	Value	Description

31-4	Reserved	0	Reserved

3	Reserved	0	Reserved. This bit must always be written with a 0.

2	ELSI		Receiver line status interrupt enable.
		0	Receiver line status interrupt is disabled.
		1	Receiver line status interrupt is enabled.

1	ETBEI		Transmitter holding register empty interrupt enable.
		0	Transmitter holding register empty interrupt is disabled.
		1	Transmitter holding register empty interrupt is enabled.

0	ERBI		Receiver data available interrupt and character timeout indication interrupt enable.
		0	Receiver data available interrupt and character timeout indication interrupt is disabled.
		1	Receiver data available interrupt and character timeout indication interrupt is enabled.

24	Universal Asynchronous Receiver/Transmitter (UART)	SPRU997C –December 2009
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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Uart Supported Features/Characteristics by InstanceFeature Support Industry Standards Compliance StatementUart Block Diagram FifoClock Generation and Control UartDlhdll BclkBaud Rate Divisor Value Actual Baud Rate Error % Baud Rate Examples for 27 MHz Uart Input ClockStart Parity STOP1 STOP2 Signal Descriptions Pin MultiplexingProtocol Description Endianness Considerations Data FormatParity STOP1 ParityOperation Fifo Modes Character Time for Word LengthsCharacter Time Four Character Times Uart Interface Using Autoflow Diagram Autoflow ControlAutoflow Functional Timing Waveforms for RTS Loopback ControlReset Considerations InitializationInterrupt Support Enable bits Uart Interrupt Requests DescriptionsUart Interrupt Request Interrupt Source CommentPower Management DMA Event SupportEmulation Considerations Changing Operating Mode During Busy Serial Communication Exception ProcessingDivisor Latch Not Programmed Uart RegistersAccess considerations Receiver Buffer Register RBRReceiver Buffer Register RBR Field Descriptions Bit FieldTransmitter Holding Register THR Transmitter Holding Register THR Field DescriptionsBit Field Value Description Interrupt Enable Register IER Interrupt Enable Register IER Field DescriptionsElsi Etbei Erbi ElsiAccess consideration Interrupt Identification Register IIRInterrupt Identification Register IIR Field Descriptions Fifo Control Register FCR Interrupt Identification and Interrupt Clearing InformationIIR Bits Interrupt Type Interrupt SourceFifo Control Register FCR Field Descriptions RxfiftlDMAMODE11 Txclr Rxclr Fifoen DMAMODE1Line Control Register LCR Line Control Register LCR Field DescriptionsDlab EPS PEN STB WLS DlabRelationship Between ST, EPS, and PEN Bits in LCR Number of Stop Bits GeneratedST Bit EPS Bit PEN Bit Parity Option STB BitModem Control Register MCR Modem Control Register MCR Field DescriptionsLoop AFENon-FIFO mode Fifo modeLine Status Register LSR Line Status Register LSR Field DescriptionsSet Elsi = 1 in IER, an interrupt request is generated Divisor Latches DLL and DLH Register RBRDivisor LSB Latch DLL Field Descriptions Divisor MSB Latch DLH Field DescriptionsPeripheral Identification Registers PID1 and PID2 CLS REVCLS TYPPower and Emulation Management Register Pwremumgmt Utrst UrrstFree UtrstDocument Revision History Reference Additions/Modifications/DeletionsImportant Notice

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