Texas Instruments TMS320DM643X DMP manual Purpose of the Peripheral, Features

Page 7

User's Guide

SPRU997C – December 2009

Universal Asynchronous Receiver/Transmitter (UART)

1Introduction

This document describes the universal asynchronous receiver/transmitter (UART) peripheral in the TMS320DM643x Digital Media Processor (DMP) .

1.1Purpose of the Peripheral

The UART peripheral is based on the industry standard TL16C550 asynchronous communications element, which in turn is a functional upgrade of the TL16C450. Functionally similar to the TL16C450 on power up (single character or TL16C450 mode), the UART can be placed in an alternate FIFO (TL16C550) mode. This relieves the CPU of excessive software overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to 16 bytes including three additional bits of error status per byte for the receiver FIFO.

The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-to-serial conversion on data received from the CPU. The CPU can read the UART status at any time. The UART includes control capability and a processor interrupt system that can be tailored to minimize software management of the communications link.

The UART includes a programmable baud generator capable of dividing the UART input clock by divisors from 1 to 65 535 and producing a 16 × reference clock for the internal transmitter and receiver logic. For detailed timing and electrical specifications for the UART, see the device specific data manual.

1.2Features

The UART peripheral has the following features:

•Programmable baud rates up to 128 kbps (frequency pre-scale values from 1 to 65535)

•Fully programmable serial interface characteristics:

–5, 6, 7, or 8-bit characters

–Even, odd, or no PARITY bit generation and detection

–1, 1.5, or 2 STOP bit generation

•16-byte depth transmitter and receiver FIFOs:

–The UART can be operated with or without the FIFOs

–1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA

•DMA signaling capability for both received and transmitted data

•CPU interrupt capability for both received and transmitted data

•Operates in little-endian mode

•False START bit detection

•Line break generation and detection

•Internal diagnostic capabilities:

–Loopback controls for communications link fault isolation

–Break, parity, overrun, and framing error simulation

•Programmable autoflow control using CTS and RTS signals (not supported on all UARTs. See the device-specific data manual for supported features.)

•Modem control functions using CTS and RTS signals (not supported on all UARTs. See the device-specific data manual for supported features.)

SPRU997C –December 2009

Universal Asynchronous Receiver/Transmitter (UART)

7

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2009, Texas Instruments Incorporated

 

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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramUart Supported Features/Characteristics by Instance Feature SupportFifo Uart Block DiagramBclk Clock Generation and ControlUart DlhdllBaud Rate Examples for 27 MHz Uart Input Clock Baud Rate Divisor Value Actual Baud Rate Error %Start Parity STOP1 STOP2 Pin Multiplexing Signal DescriptionsProtocol Description Parity Endianness ConsiderationsData Format Parity STOP1Operation Character Time for Word Lengths Fifo ModesCharacter Time Four Character Times Autoflow Control Uart Interface Using Autoflow DiagramLoopback Control Autoflow Functional Timing Waveforms for RTSInitialization Reset ConsiderationsInterrupt Support Comment Enable bitsUart Interrupt Requests Descriptions Uart Interrupt Request Interrupt SourceDMA Event Support Power ManagementEmulation Considerations Uart Registers Changing Operating Mode During Busy Serial CommunicationException Processing Divisor Latch Not ProgrammedBit Field Access considerationsReceiver Buffer Register RBR Receiver Buffer Register RBR Field DescriptionsTransmitter Holding Register THR Field Descriptions Transmitter Holding Register THRBit Field Value Description Elsi Interrupt Enable Register IERInterrupt Enable Register IER Field Descriptions Elsi Etbei ErbiInterrupt Identification Register IIR Access considerationInterrupt Identification Register IIR Field Descriptions Interrupt Type Interrupt Source Fifo Control Register FCRInterrupt Identification and Interrupt Clearing Information IIR BitsDMAMODE1 Fifo Control Register FCR Field DescriptionsRxfiftl DMAMODE11 Txclr Rxclr FifoenDlab Line Control Register LCRLine Control Register LCR Field Descriptions Dlab EPS PEN STB WLSSTB Bit Relationship Between ST, EPS, and PEN Bits in LCRNumber of Stop Bits Generated ST Bit EPS Bit PEN Bit Parity OptionAFE Modem Control Register MCRModem Control Register MCR Field Descriptions LoopLine Status Register LSR Field Descriptions Non-FIFO modeFifo mode Line Status Register LSRSet Elsi = 1 in IER, an interrupt request is generated Register RBR Divisor Latches DLL and DLHDivisor MSB Latch DLH Field Descriptions Divisor LSB Latch DLL Field DescriptionsTYP Peripheral Identification Registers PID1 and PID2CLS REV CLSUtrst Power and Emulation Management Register PwremumgmtUtrst Urrst FreeReference Additions/Modifications/Deletions Document Revision HistoryImportant Notice
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