Texas Instruments TMS320DM643X DMP Transmitter Holding Register THR, Bit Field Value Description

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Registers

3.2Transmitter Holding Register (THR)

The transmitter holding register (THR) is shown in Figure 10 and described in Table 8.

The UART transmitter section consists of a transmitter hold register (THR) and a transmitter shift register (TSR). When the UART is in the FIFO mode, THR is a 16-byte FIFO. Transmitter section control is a function of the line control register (LCR).

THR receives data from the internal data bus and when TSR is idle, the UART moves the data from THR to TSR. The UART serializes the data in TSR and transmits the data on the TX pin. In the non-FIFO mode, if THR is empty and the THR empty (THRE) interrupt is enabled (ETBEI = 1 in IER), an interrupt is generated. This interrupt is cleared when a character is loaded into THR. In the FIFO mode, the interrupt is generated when the transmitter FIFO is empty, and it is cleared when at least one byte is loaded into the FIFO.

Access considerations:

RBR, THR, and DLL share one address. To load THR, write 0 to the DLAB bit of LCR, and write to the shared address. When DLAB = 0, reading from the shared address gives the content of RBR. When DLAB = 1, all accesses at the address read or modify DLL.

DLL also has a dedicated address. If you use the dedicated address, you can keep DLAB = 0, so that RBR and THR are always selected at the shared address.

Figure 10. Transmitter Holding Register (THR)

31				16
	Reserved

		R-0
15	8	7		0

	Reserved			DATA
	R-0			W-0

LEGEND: R = Read only; W = Write only; -n= value after reset

Table 8. Transmitter Holding Register (THR) Field Descriptions

Bit	Field	Value	Description

31-8	Reserved	0	Reserved

7-0	DATA	0-FFh	Data to transmit

SPRU997C –December 2009	Universal Asynchronous Receiver/Transmitter (UART)	23
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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramUart Supported Features/Characteristics by Instance Feature SupportFifo Uart Block DiagramBclk Clock Generation and ControlUart DlhdllStart Parity STOP1 STOP2 Baud Rate Divisor Value Actual Baud Rate Error %Baud Rate Examples for 27 MHz Uart Input Clock Protocol Description Signal DescriptionsPin Multiplexing Parity Endianness ConsiderationsData Format Parity STOP1Operation Character Time Four Character Times Fifo ModesCharacter Time for Word Lengths Autoflow Control Uart Interface Using Autoflow DiagramLoopback Control Autoflow Functional Timing Waveforms for RTSInterrupt Support Reset ConsiderationsInitialization Comment Enable bitsUart Interrupt Requests Descriptions Uart Interrupt Request Interrupt SourceEmulation Considerations Power ManagementDMA Event Support Uart Registers Changing Operating Mode During Busy Serial CommunicationException Processing Divisor Latch Not ProgrammedBit Field Access considerationsReceiver Buffer Register RBR Receiver Buffer Register RBR Field DescriptionsBit Field Value Description Transmitter Holding Register THRTransmitter Holding Register THR Field Descriptions Elsi Interrupt Enable Register IERInterrupt Enable Register IER Field Descriptions Elsi Etbei ErbiInterrupt Identification Register IIR Field Descriptions Access considerationInterrupt Identification Register IIR Interrupt Type Interrupt Source Fifo Control Register FCRInterrupt Identification and Interrupt Clearing Information IIR BitsDMAMODE1 Fifo Control Register FCR Field DescriptionsRxfiftl DMAMODE11 Txclr Rxclr FifoenDlab Line Control Register LCRLine Control Register LCR Field Descriptions Dlab EPS PEN STB WLSSTB Bit Relationship Between ST, EPS, and PEN Bits in LCRNumber of Stop Bits Generated ST Bit EPS Bit PEN Bit Parity OptionAFE Modem Control Register MCRModem Control Register MCR Field Descriptions LoopLine Status Register LSR Field Descriptions Non-FIFO modeFifo mode Line Status Register LSRSet Elsi = 1 in IER, an interrupt request is generated Register RBR Divisor Latches DLL and DLHDivisor MSB Latch DLH Field Descriptions Divisor LSB Latch DLL Field DescriptionsTYP Peripheral Identification Registers PID1 and PID2CLS REV CLSUtrst Power and Emulation Management Register PwremumgmtUtrst Urrst FreeReference Additions/Modifications/Deletions Document Revision HistoryImportant Notice

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