Texas Instruments TMS320DM643X DMP manual List of Tables

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	List of Tables
1	UART Supported Features/Characteristics by Instance	8
2	Baud Rate Examples for 27 MHz UART Input Clock	11
3	UART Signal Descriptions	12
4	Character Time for Word Lengths	15
5	UART Interrupt Requests Descriptions	19
6	UART Registers	21
7	Receiver Buffer Register (RBR) Field Descriptions	22
8	Transmitter Holding Register (THR) Field Descriptions	23
9	Interrupt Enable Register (IER) Field Descriptions	24
10	Interrupt Identification Register (IIR) Field Descriptions	25
11	Interrupt Identification and Interrupt Clearing Information	26
12	FIFO Control Register (FCR) Field Descriptions	27
13	Line Control Register (LCR) Field Descriptions	28
14	Relationship Between ST, EPS, and PEN Bits in LCR	29
15	Number of STOP Bits Generated	29
16	Modem Control Register (MCR) Field Descriptions	30
17	Line Status Register (LSR) Field Descriptions	31
18	Divisor LSB Latch (DLL) Field Descriptions	34
19	Divisor MSB Latch (DLH) Field Descriptions	34
20	Peripheral Identification Register 1 (PID1) Field Descriptions	35
21	Peripheral Identification Register 2 (PID2) Field Descriptions	35
22	Power and Emulation Management Register (PWREMU_MGMT) Field Descriptions	36
23	Document Revision History	37

SPRU997C –December 2009	List of Tables	5
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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesUart Supported Features/Characteristics by Instance Functional Block DiagramFeature Support Industry Standards Compliance StatementFifo Uart Block DiagramUart Clock Generation and ControlDlhdll BclkStart Parity STOP1 STOP2 Baud Rate Divisor Value Actual Baud Rate Error %Baud Rate Examples for 27 MHz Uart Input Clock Protocol Description Signal DescriptionsPin Multiplexing Data Format Endianness ConsiderationsParity STOP1 ParityOperation Character Time Four Character Times Fifo ModesCharacter Time for Word Lengths Autoflow Control Uart Interface Using Autoflow DiagramLoopback Control Autoflow Functional Timing Waveforms for RTSInterrupt Support Reset ConsiderationsInitialization Uart Interrupt Requests Descriptions Enable bitsUart Interrupt Request Interrupt Source CommentEmulation Considerations Power ManagementDMA Event Support Exception Processing Changing Operating Mode During Busy Serial CommunicationDivisor Latch Not Programmed Uart RegistersReceiver Buffer Register RBR Access considerationsReceiver Buffer Register RBR Field Descriptions Bit FieldBit Field Value Description Transmitter Holding Register THRTransmitter Holding Register THR Field Descriptions Interrupt Enable Register IER Field Descriptions Interrupt Enable Register IERElsi Etbei Erbi ElsiInterrupt Identification Register IIR Field Descriptions Access considerationInterrupt Identification Register IIR Interrupt Identification and Interrupt Clearing Information Fifo Control Register FCRIIR Bits Interrupt Type Interrupt SourceRxfiftl Fifo Control Register FCR Field DescriptionsDMAMODE11 Txclr Rxclr Fifoen DMAMODE1Line Control Register LCR Field Descriptions Line Control Register LCRDlab EPS PEN STB WLS DlabNumber of Stop Bits Generated Relationship Between ST, EPS, and PEN Bits in LCRST Bit EPS Bit PEN Bit Parity Option STB BitModem Control Register MCR Field Descriptions Modem Control Register MCRLoop AFEFifo mode Non-FIFO modeLine Status Register LSR Line Status Register LSR Field DescriptionsSet Elsi = 1 in IER, an interrupt request is generated Register RBR Divisor Latches DLL and DLHDivisor MSB Latch DLH Field Descriptions Divisor LSB Latch DLL Field DescriptionsCLS REV Peripheral Identification Registers PID1 and PID2CLS TYPUtrst Urrst Power and Emulation Management Register PwremumgmtFree UtrstReference Additions/Modifications/Deletions Document Revision HistoryImportant Notice

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