Texas Instruments TMS320DM643X DMP manual Autoflow Control, Uart Interface Using Autoflow Diagram

Page 16

Peripheral Architecture

www.ti.com

2.6.3.2FIFO Poll Mode

When the receiver FIFO is enabled in the FIFO control register (FCR) and the receiver interrupts are disabled in the interrupt enable register (IER), the poll mode is selected for the receiver FIFO. Similarly, when the transmitter FIFO is enabled and the transmitter interrupts are disabled, the transmitted FIFO is in the poll mode. In the poll mode, the CPU detects events by checking bits in the line status register (LSR):

•The RXFIFOE bit indicates whether there are any errors in the receiver FIFO.

•The TEMT bit indicates that both the transmitter holding register (THR) and the transmitter shift register (TSR) are empty.

•The THRE bit indicates when THR is empty.

•The BI (break), FE (framing error), PE (parity error), and OE (overrun error) bits specify which error or errors have occurred.

•The DR (data-ready) bit is set as long as there is at least one byte in the receiver FIFO.

Also, in the FIFO poll mode:

•The interrupt identification register (IIR) is not affected by any events because the interrupts are disabled.

•The UART does not indicate when the receiver FIFO trigger level is reached or when a receiver time-out occurs.

2.6.4Autoflow Control

The UART can employ autoflow control by connecting the CTS and RTS signals. Note that all UARTs do not support autoflow control, see the device-specific data manual for supported features. The CTS input must be active before the transmitter FIFO can transmit data. The RTS becomes active when the receiver needs more data and notifies the sending device. When RTS is connected to CTS, data transmission does not occur unless the receiver FIFO has space for the data. Therefore, when two UARTs are connected as shown in Figure 5 with autoflow enabled, overrun errors are eliminated.

Figure 5. UART Interface Using Autoflow Diagram

UART

 

 

 

 

UART

 

Serial to

rx

tx

Parallel to

 

 

Parallel

Serial

 

Receiver

 

 

Transmitter

 

 

 

 

FIFO

Flow

rts cts

Flow

FIFO

 

 

D[7:0]

Control

 

 

Control

 

 

 

 

 

D[7:0]

 

Parallel to

tx

rx

Serial to

 

 

Transmitter

Serial

 

 

Parallel

Receiver

 

 

 

 

FIFO

Flow

cts rts

Flow

FIFO

 

 

 

Control

 

 

Control

 

DMP

 

 

 

 

Off-chip

16

Universal Asynchronous Receiver/Transmitter (UART)

SPRU997C –December 2009

Submit Documentation Feedback

Copyright © 2009, Texas Instruments Incorporated

Page 15 Page 17
Image 16
Page 15 Page 17
Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Uart Supported Features/Characteristics by InstanceFeature Support Industry Standards Compliance StatementUart Block Diagram FifoClock Generation and Control UartDlhdll BclkBaud Rate Examples for 27 MHz Uart Input Clock Baud Rate Divisor Value Actual Baud Rate Error %Start Parity STOP1 STOP2 Pin Multiplexing Signal DescriptionsProtocol Description Endianness Considerations Data FormatParity STOP1 ParityOperation Character Time for Word Lengths Fifo ModesCharacter Time Four Character Times Uart Interface Using Autoflow Diagram Autoflow ControlAutoflow Functional Timing Waveforms for RTS Loopback ControlInitialization Reset ConsiderationsInterrupt Support Enable bits Uart Interrupt Requests DescriptionsUart Interrupt Request Interrupt Source CommentDMA Event Support Power ManagementEmulation Considerations Changing Operating Mode During Busy Serial Communication Exception ProcessingDivisor Latch Not Programmed Uart RegistersAccess considerations Receiver Buffer Register RBRReceiver Buffer Register RBR Field Descriptions Bit FieldTransmitter Holding Register THR Field Descriptions Transmitter Holding Register THRBit Field Value Description Interrupt Enable Register IER Interrupt Enable Register IER Field DescriptionsElsi Etbei Erbi ElsiInterrupt Identification Register IIR Access considerationInterrupt Identification Register IIR Field Descriptions Fifo Control Register FCR Interrupt Identification and Interrupt Clearing InformationIIR Bits Interrupt Type Interrupt SourceFifo Control Register FCR Field Descriptions RxfiftlDMAMODE11 Txclr Rxclr Fifoen DMAMODE1Line Control Register LCR Line Control Register LCR Field DescriptionsDlab EPS PEN STB WLS DlabRelationship Between ST, EPS, and PEN Bits in LCR Number of Stop Bits GeneratedST Bit EPS Bit PEN Bit Parity Option STB BitModem Control Register MCR Modem Control Register MCR Field DescriptionsLoop AFENon-FIFO mode Fifo modeLine Status Register LSR Line Status Register LSR Field DescriptionsSet Elsi = 1 in IER, an interrupt request is generated Divisor Latches DLL and DLH Register RBRDivisor LSB Latch DLL Field Descriptions Divisor MSB Latch DLH Field DescriptionsPeripheral Identification Registers PID1 and PID2 CLS REVCLS TYPPower and Emulation Management Register Pwremumgmt Utrst UrrstFree UtrstDocument Revision History Reference Additions/Modifications/DeletionsImportant Notice
Related manuals
Manual 120 pages 29.22 Kb
Top Page Image Contents