Texas Instruments TMS320DM643X DMP DMA Event Support, Power Management, Emulation Considerations

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Peripheral Architecture

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2.10 DMA Event Support

In the FIFO mode, the UART generates the following two DMA events:

•Receive event (URXEVT): The trigger level for the receiver FIFO (1, 4, 8, or 14 characters) is set with the RXFIFTL bit in the FIFO control register (FCR). Every time the trigger level is reached or a receiver time-out occurs, the UART sends a receive event to the EDMA controller. In response, the EDMA controller reads the data from the receiver FIFO by way of the receiver buffer register (RBR). Note that the receive event is not asserted if the data at the top of the receiver FIFO is erroneous even if the trigger level has been reached.

•Transmit event (UTXEVT): When the transmitter FIFO is empty (when the last byte in the transmitter FIFO has been copied to the transmitter shift register), the UART sends an UTXEVT signal to the EDMA controller. In response, the EDMA controller refills the transmitter FIFO by way of the transmitter holding register (THR). The UTXEVT signal is also sent to the DMA controller when the UART is taken out of reset using the UTRST bit in the power and emulation management register (PWREMU_MGMT).

Activity in DMA channels can be synchronized to these events. In the non-FIFO mode, the UART generates no DMA events. Any DMA channel synchronized to either of these events must be enabled at the time the UART event is generated. Otherwise, the DMA channel will miss the event and, unless the UART generates a new event, no data transfer will occur.

2.11 Power Management

The UART peripheral can be placed in reduced-power modes to conserve power during periods of low activity. The power management of the UART peripheral is controlled by the processor Power and Sleep Controller (PSC). The PSC acts as a master controller for power management for all of the peripherals on the device. For detailed information on power management procedures using the PSC, see the TMS320DM643x DMP DSP Subsystem Reference Guide (SPRU978).

2.12 Emulation Considerations

The FREE bit in the power and emulation management register (PWREMU_MGMT) determines how the UART responds to an emulation suspend event such as an emulator halt or breakpoint. If FREE = 0 and a transmission is in progress, the UART halts after completing the one-word transmission; if FREE = 0 and a transmission is not in progress, the UART halts immediately. If FREE = 1, the UART does not halt and continues operating normally.

Note also that emulator accesses are essentially transparent to UART operation. Emulator read operations do not affect any register contents, status bits, or operating states. Emulator writes, however, may affect register contents and may affect UART operation, depending on what register is accessed and what value is written.

The UART registers can be read from or written to during emulation suspend events, even if the UART activity has stopped.

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Universal Asynchronous Receiver/Transmitter (UART)

SPRU997C –December 2009

 

 

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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Uart Supported Features/Characteristics by InstanceFeature Support Industry Standards Compliance StatementUart Block Diagram FifoClock Generation and Control UartDlhdll BclkStart Parity STOP1 STOP2 Baud Rate Divisor Value Actual Baud Rate Error %Baud Rate Examples for 27 MHz Uart Input Clock Protocol Description Signal DescriptionsPin Multiplexing Endianness Considerations Data FormatParity STOP1 ParityOperation Character Time Four Character Times Fifo ModesCharacter Time for Word Lengths Uart Interface Using Autoflow Diagram Autoflow ControlAutoflow Functional Timing Waveforms for RTS Loopback ControlInterrupt Support Reset ConsiderationsInitialization Enable bits Uart Interrupt Requests DescriptionsUart Interrupt Request Interrupt Source CommentEmulation Considerations Power ManagementDMA Event Support Changing Operating Mode During Busy Serial Communication Exception ProcessingDivisor Latch Not Programmed Uart RegistersAccess considerations Receiver Buffer Register RBRReceiver Buffer Register RBR Field Descriptions Bit FieldBit Field Value Description Transmitter Holding Register THRTransmitter Holding Register THR Field Descriptions Interrupt Enable Register IER Interrupt Enable Register IER Field DescriptionsElsi Etbei Erbi ElsiInterrupt Identification Register IIR Field Descriptions Access considerationInterrupt Identification Register IIR Fifo Control Register FCR Interrupt Identification and Interrupt Clearing InformationIIR Bits Interrupt Type Interrupt SourceFifo Control Register FCR Field Descriptions RxfiftlDMAMODE11 Txclr Rxclr Fifoen DMAMODE1Line Control Register LCR Line Control Register LCR Field DescriptionsDlab EPS PEN STB WLS DlabRelationship Between ST, EPS, and PEN Bits in LCR Number of Stop Bits GeneratedST Bit EPS Bit PEN Bit Parity Option STB BitModem Control Register MCR Modem Control Register MCR Field DescriptionsLoop AFENon-FIFO mode Fifo modeLine Status Register LSR Line Status Register LSR Field DescriptionsSet Elsi = 1 in IER, an interrupt request is generated Divisor Latches DLL and DLH Register RBRDivisor LSB Latch DLL Field Descriptions Divisor MSB Latch DLH Field DescriptionsPeripheral Identification Registers PID1 and PID2 CLS REVCLS TYPPower and Emulation Management Register Pwremumgmt Utrst UrrstFree UtrstDocument Revision History Reference Additions/Modifications/DeletionsImportant Notice
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