Texas Instruments TMS320DM643X DMP Peripheral Identification Registers PID1 and PID2, Cls Rev

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Registers

3.10 Peripheral Identification Registers (PID1 and PID2)

The peripheral identification registers (PID) contain identification data (class, revision, and type) for the peripheral. PID1 is shown in Figure 19 and described in Table 20. PID2 is shown in Figure 20 and described in Table 21.

Figure 19. Peripheral Identification Register 1 (PID1)

31				16
	Reserved

		R-0
15	8	7		0

	CLS			REV

	R-1h			R-1h

LEGEND: R = Read only; -n= value after reset

Table 20. Peripheral Identification Register 1 (PID1) Field Descriptions

Bit	Field	Value	Description

31-16	Reserved	0	Reserved

15-8	CLS		Identifies class of peripheral.
		1	Serial port

7-0	REV		Identifies revision of peripheral.
		1	Current revision of peripheral.

Figure 20. Peripheral Identification Register 2 (PID2)

31				16
	Reserved

		R-0
15	8	7		0

	Reserved			TYP

	R-0			R-04h

LEGEND: R = Read only; -n= value after reset

Table 21. Peripheral Identification Register 2 (PID2) Field Descriptions

Bit	Field	Value	Description

31-8	Reserved	0	Reserved

7-0	TYP		Identifies type of peripheral.
		4h	UART

SPRU997C –December 2009	Universal Asynchronous Receiver/Transmitter (UART)	35
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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramUart Supported Features/Characteristics by Instance Feature SupportFifo Uart Block DiagramBclk Clock Generation and ControlUart DlhdllStart Parity STOP1 STOP2 Baud Rate Divisor Value Actual Baud Rate Error %Baud Rate Examples for 27 MHz Uart Input Clock Protocol Description Signal DescriptionsPin Multiplexing Parity Endianness ConsiderationsData Format Parity STOP1Operation Character Time Four Character Times Fifo ModesCharacter Time for Word Lengths Autoflow Control Uart Interface Using Autoflow DiagramLoopback Control Autoflow Functional Timing Waveforms for RTSInterrupt Support Reset ConsiderationsInitialization Comment Enable bitsUart Interrupt Requests Descriptions Uart Interrupt Request Interrupt SourceEmulation Considerations Power ManagementDMA Event Support Uart Registers Changing Operating Mode During Busy Serial CommunicationException Processing Divisor Latch Not ProgrammedBit Field Access considerationsReceiver Buffer Register RBR Receiver Buffer Register RBR Field DescriptionsBit Field Value Description Transmitter Holding Register THRTransmitter Holding Register THR Field Descriptions Elsi Interrupt Enable Register IERInterrupt Enable Register IER Field Descriptions Elsi Etbei ErbiInterrupt Identification Register IIR Field Descriptions Access considerationInterrupt Identification Register IIR Interrupt Type Interrupt Source Fifo Control Register FCRInterrupt Identification and Interrupt Clearing Information IIR BitsDMAMODE1 Fifo Control Register FCR Field DescriptionsRxfiftl DMAMODE11 Txclr Rxclr FifoenDlab Line Control Register LCRLine Control Register LCR Field Descriptions Dlab EPS PEN STB WLSSTB Bit Relationship Between ST, EPS, and PEN Bits in LCRNumber of Stop Bits Generated ST Bit EPS Bit PEN Bit Parity OptionAFE Modem Control Register MCRModem Control Register MCR Field Descriptions LoopLine Status Register LSR Field Descriptions Non-FIFO modeFifo mode Line Status Register LSRSet Elsi = 1 in IER, an interrupt request is generated Register RBR Divisor Latches DLL and DLHDivisor MSB Latch DLH Field Descriptions Divisor LSB Latch DLL Field DescriptionsTYP Peripheral Identification Registers PID1 and PID2CLS REV CLSUtrst Power and Emulation Management Register PwremumgmtUtrst Urrst FreeReference Additions/Modifications/Deletions Document Revision HistoryImportant Notice

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