Texas Instruments TMS320DM643X DMP manual Set Elsi = 1 in IER, an interrupt request is generated

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Table 17. Line Status Register (LSR) Field Descriptions (continued)

Bit	Field	Value Description
4	BI	Break indicator. The BI bit is set whenever the receive data input (RX) was held low for longer than a
		full-word transmission time. A full-word transmission time is defined as the total time to transmit the
		START, data, PARITY, and STOP bits. If the BI bit is set and the corresponding interrupt enable bit is
		set (ELSI = 1 in IER), an interrupt request is generated.

			In non-FIFO mode:
	0		No break has been detected, or the BI bit was cleared because the CPU read the erroneous character
			from the receiver buffer register (RBR).
	1		A break has been detected with the character in the receiver buffer register (RBR).

			In FIFO mode:
	0		No break has been detected, or the BI bit was cleared because the CPU read the erroneous character
			from the receiver FIFO and the next character to be read from the FIFO has no break indicator.
	1		A break has been detected with the character at the top of the receiver FIFO.

3	FE		Framing error (FE) indicator. A framing error occurs when the received character does not have a valid
			STOP bit. In response to a framing error, the UART sets the FE bit and waits until the signal on the RX
			pin goes high. Once the RX signal goes high, the receiver is ready to detect a new START bit and
			receive new data. If the FE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER),
			an interrupt request is generated.
			In non-FIFO mode:
	0		No framing error has been detected, or the FE bit was cleared because the CPU read the erroneous
			data from the receiver buffer register (RBR).
	1		A framing error has been detected with the character in the receiver buffer register (RBR).

			In FIFO mode:
	0		No framing error has been detected, or the FE bit was cleared because the CPU read the erroneous
			data from the receiver FIFO and the next character to be read from the FIFO has no framing error.
	1		A framing error has been detected with the character at the top of the receiver FIFO.

2	PE		Parity error (PE) indicator. A parity error occurs when the parity of the received character does not
			match the parity selected with the EPS bit in the line control register (LCR). If the PE bit is set and the
			corresponding interrupt enable bit is set (ELSI = 1 in IER), an interrupt request is generated.
			In non-FIFO mode:
	0		No parity error has been detected, or the PE bit was cleared because the CPU read the erroneous data
			from the receiver buffer register (RBR).
	1		A parity error has been detected with the character in the receiver buffer register (RBR).

			In FIFO mode:
	0		No parity error has been detected, or the PE bit was cleared because the CPU read the erroneous data
			from the receiver FIFO and the next character to be read from the FIFO has no parity error.
	1		A parity error has been detected with the character at the top of the receiver FIFO.

1	OE		Overrun error (OE) indicator. An overrun error in the non-FIFO mode is different from an overrun error
			in the FIFO mode. If the OE bit is set and the corresponding interrupt enable bit is set (ELSI = 1 in IER),
			an interrupt request is generated.
			In non-FIFO mode:
	0		No overrun error has been detected, or the OE bit was cleared because the CPU read the content of
			the line status register (LSR).
	1		Overrun error has been detected. Before the character in the receiver buffer register (RBR) could be
			read, it was overwritten by the next character arriving in RBR.

			In FIFO mode:
	0		No overrun error has been detected, or the OE bit was cleared because the CPU read the content of
			the line status register (LSR).
	1		Overrun error has been detected. If data continues to fill the FIFO beyond the trigger level, an overrun
			error occurs only after the FIFO is full and the next character has been completely received in the shift
			register. An overrun error is indicated to the CPU as soon as it happens. The new character overwrites
			the character in the shift register, but it is not transferred to the FIFO.

32	Universal Asynchronous Receiver/Transmitter (UART)	SPRU997C –December 2009
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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Features Purpose of the PeripheralFunctional Block Diagram Uart Supported Features/Characteristics by InstanceFeature Support Industry Standards Compliance StatementUart Block Diagram FifoClock Generation and Control UartDlhdll BclkStart Parity STOP1 STOP2 Baud Rate Divisor Value Actual Baud Rate Error %Baud Rate Examples for 27 MHz Uart Input Clock Protocol Description Signal DescriptionsPin Multiplexing Endianness Considerations Data FormatParity STOP1 ParityOperation Character Time Four Character Times Fifo ModesCharacter Time for Word Lengths Uart Interface Using Autoflow Diagram Autoflow ControlAutoflow Functional Timing Waveforms for RTS Loopback ControlInterrupt Support Reset ConsiderationsInitialization Enable bits Uart Interrupt Requests DescriptionsUart Interrupt Request Interrupt Source CommentEmulation Considerations Power ManagementDMA Event Support Changing Operating Mode During Busy Serial Communication Exception ProcessingDivisor Latch Not Programmed Uart RegistersAccess considerations Receiver Buffer Register RBRReceiver Buffer Register RBR Field Descriptions Bit FieldBit Field Value Description Transmitter Holding Register THRTransmitter Holding Register THR Field Descriptions Interrupt Enable Register IER Interrupt Enable Register IER Field DescriptionsElsi Etbei Erbi ElsiInterrupt Identification Register IIR Field Descriptions Access considerationInterrupt Identification Register IIR Fifo Control Register FCR Interrupt Identification and Interrupt Clearing InformationIIR Bits Interrupt Type Interrupt SourceFifo Control Register FCR Field Descriptions RxfiftlDMAMODE11 Txclr Rxclr Fifoen DMAMODE1Line Control Register LCR Line Control Register LCR Field DescriptionsDlab EPS PEN STB WLS DlabRelationship Between ST, EPS, and PEN Bits in LCR Number of Stop Bits GeneratedST Bit EPS Bit PEN Bit Parity Option STB BitModem Control Register MCR Modem Control Register MCR Field DescriptionsLoop AFENon-FIFO mode Fifo modeLine Status Register LSR Line Status Register LSR Field DescriptionsSet Elsi = 1 in IER, an interrupt request is generated Divisor Latches DLL and DLH Register RBRDivisor LSB Latch DLL Field Descriptions Divisor MSB Latch DLH Field DescriptionsPeripheral Identification Registers PID1 and PID2 CLS REVCLS TYPPower and Emulation Management Register Pwremumgmt Utrst UrrstFree UtrstDocument Revision History Reference Additions/Modifications/DeletionsImportant Notice

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