Texas Instruments TMS320DM643X DMP manual Endianness Considerations, Data Format, Parity STOP1

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Peripheral Architecture

2.4.3Data Format

The UART transmits in the following format:

1 START bit + data bits (5, 6, 7, 8) + 1 PARITY bit (optional) + STOP bit (1, 1.5, 2)

It transmits 1 START bit; 5, 6, 7, or 8 data bits, depending on the data width selection; 1 PARITY bit, if parity is selected; and 1, 1.5, or 2 STOP bits, depending on the STOP bit selection.

The UART receives in the following format:

1 START bit + data bits (5, 6, 7, 8) + 1 PARITY bit (optional) + STOP bit (1)

It receives 1 START bit; 5, 6, 7, or 8 data bits, depending on the data width selection; 1 PARITY bit, if parity is selected; and 1 STOP bit.

The protocol formats are shown in Figure 4

Figure 4. UART Protocol Formats

		D0	D1		D2	D3	D4	PARITY	STOP1

				Transmit/Receive for 5-bit data, parity Enable, 1 STOP bit

		D0	D1		D2	D3	D4	D5	PARITY
				Transmit/Receive for 6-bit data, parity Enable, 1 STOP bit

STOP1

		D0	D1		D2	D3	D4	D5	D6	PARITY
				Transmit/Receive for 7-bit data, parity Enable, 1 STOP bit

STOP1

		D0	D1		D2	D3	D4	D5	D6	D7	PARITY
				Transmit/Receive for 8-bit data, parity Enable, 1 STOP bit

STOP1

2.5Endianness Considerations

Since the UART transfers 8-bit data externally, and proper endianness is maintained automatically within the DM643x DMP, there are no endianness considerations when using the DM643x UART peripheral.

SPRU997C –December 2009	Universal Asynchronous Receiver/Transmitter (UART)	13
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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesUart Supported Features/Characteristics by Instance Functional Block DiagramFeature Support Industry Standards Compliance StatementFifo Uart Block DiagramUart Clock Generation and ControlDlhdll BclkBaud Rate Examples for 27 MHz Uart Input Clock Baud Rate Divisor Value Actual Baud Rate Error %Start Parity STOP1 STOP2 Pin Multiplexing Signal DescriptionsProtocol Description Data Format Endianness ConsiderationsParity STOP1 ParityOperation Character Time for Word Lengths Fifo ModesCharacter Time Four Character Times Autoflow Control Uart Interface Using Autoflow DiagramLoopback Control Autoflow Functional Timing Waveforms for RTSInitialization Reset ConsiderationsInterrupt Support Uart Interrupt Requests Descriptions Enable bitsUart Interrupt Request Interrupt Source CommentDMA Event Support Power ManagementEmulation Considerations Exception Processing Changing Operating Mode During Busy Serial CommunicationDivisor Latch Not Programmed Uart RegistersReceiver Buffer Register RBR Access considerationsReceiver Buffer Register RBR Field Descriptions Bit FieldTransmitter Holding Register THR Field Descriptions Transmitter Holding Register THRBit Field Value Description Interrupt Enable Register IER Field Descriptions Interrupt Enable Register IERElsi Etbei Erbi ElsiInterrupt Identification Register IIR Access considerationInterrupt Identification Register IIR Field Descriptions Interrupt Identification and Interrupt Clearing Information Fifo Control Register FCRIIR Bits Interrupt Type Interrupt SourceRxfiftl Fifo Control Register FCR Field DescriptionsDMAMODE11 Txclr Rxclr Fifoen DMAMODE1Line Control Register LCR Field Descriptions Line Control Register LCRDlab EPS PEN STB WLS DlabNumber of Stop Bits Generated Relationship Between ST, EPS, and PEN Bits in LCRST Bit EPS Bit PEN Bit Parity Option STB BitModem Control Register MCR Field Descriptions Modem Control Register MCRLoop AFEFifo mode Non-FIFO modeLine Status Register LSR Line Status Register LSR Field DescriptionsSet Elsi = 1 in IER, an interrupt request is generated Register RBR Divisor Latches DLL and DLHDivisor MSB Latch DLH Field Descriptions Divisor LSB Latch DLL Field DescriptionsCLS REV Peripheral Identification Registers PID1 and PID2CLS TYPUtrst Urrst Power and Emulation Management Register PwremumgmtFree UtrstReference Additions/Modifications/Deletions Document Revision HistoryImportant Notice

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