Texas Instruments
TMS320DM643X DMP
manual
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Functional Block Diagram
Signal Descriptions
Reset Considerations
Access considerations
Power Management
Features
Enable bits
Non-FIFO mode
Page 2
2
SPRU997C
–December
2009
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Copyright © 2009, Texas Instruments Incorporated
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Contents
Users Guide
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Revision History
Appendix a
List of Figures
List of Tables
Read This First
Features
Purpose of the Peripheral
Feature Support
Functional Block Diagram
Uart Supported Features/Characteristics by Instance
Industry Standards Compliance Statement
Uart Block Diagram
Fifo
Dlhdll
Clock Generation and Control
Uart
Bclk
Start Parity STOP1 STOP2
Baud Rate Divisor Value Actual Baud Rate Error %
Baud Rate Examples for 27 MHz Uart Input Clock
Protocol Description
Signal Descriptions
Pin Multiplexing
Parity STOP1
Endianness Considerations
Data Format
Parity
Operation
Character Time Four Character Times
Fifo Modes
Character Time for Word Lengths
Uart Interface Using Autoflow Diagram
Autoflow Control
Autoflow Functional Timing Waveforms for RTS
Loopback Control
Interrupt Support
Reset Considerations
Initialization
Uart Interrupt Request Interrupt Source
Enable bits
Uart Interrupt Requests Descriptions
Comment
Emulation Considerations
Power Management
DMA Event Support
Divisor Latch Not Programmed
Changing Operating Mode During Busy Serial Communication
Exception Processing
Uart Registers
Receiver Buffer Register RBR Field Descriptions
Access considerations
Receiver Buffer Register RBR
Bit Field
Bit Field Value Description
Transmitter Holding Register THR
Transmitter Holding Register THR Field Descriptions
Elsi Etbei Erbi
Interrupt Enable Register IER
Interrupt Enable Register IER Field Descriptions
Elsi
Interrupt Identification Register IIR Field Descriptions
Access consideration
Interrupt Identification Register IIR
IIR Bits
Fifo Control Register FCR
Interrupt Identification and Interrupt Clearing Information
Interrupt Type Interrupt Source
DMAMODE11 Txclr Rxclr Fifoen
Fifo Control Register FCR Field Descriptions
Rxfiftl
DMAMODE1
Dlab EPS PEN STB WLS
Line Control Register LCR
Line Control Register LCR Field Descriptions
Dlab
ST Bit EPS Bit PEN Bit Parity Option
Relationship Between ST, EPS, and PEN Bits in LCR
Number of Stop Bits Generated
STB Bit
Loop
Modem Control Register MCR
Modem Control Register MCR Field Descriptions
AFE
Line Status Register LSR
Non-FIFO mode
Fifo mode
Line Status Register LSR Field Descriptions
Set Elsi = 1 in IER, an interrupt request is generated
Divisor Latches DLL and DLH
Register RBR
Divisor LSB Latch DLL Field Descriptions
Divisor MSB Latch DLH Field Descriptions
CLS
Peripheral Identification Registers PID1 and PID2
CLS REV
TYP
Free
Power and Emulation Management Register Pwremumgmt
Utrst Urrst
Utrst
Document Revision History
Reference Additions/Modifications/Deletions
Important Notice
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