Texas Instruments TMS320DM643X DMP manual Modem Control Register MCR, Loop, Afe, Rts

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Registers

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3.7Modem Control Register (MCR)

The modem control register (MCR) is shown in Figure 15 and described in Table 16. The modem control register provides the ability to enable/disable the autoflow functions, and enable/disable the loopback function for diagnostic purposes.

Figure 15. Modem Control Register (MCR)

31							16
	Reserved

	R-0
15	6	5	4	3	2	1	0

Reserved		AFE(1)	LOOP	Reserved		RTS(1)	Rsvd
R-0		R/W-0	R/W-0		R-0	R/W-0	R-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

(1)All UARTs do not support this feature, see the device-specific data manual for supported features. If this feature is not available, this bit is reserved and should be cleared to 0.

			Table 16. Modem Control Register (MCR) Field Descriptions

Bit	Field	Value		Description

31-6	Reserved	0		Reserved

5	AFE			Autoflow control enable. Autoflow control allows the RTS and CTS signals to provide handshaking
				between UARTs during data transfer. When AFE = 1, the RTS bit determines the autoflow control
				enabled. Note that all UARTs do not support this feature, see the device-specific data manual for
				supported features. If this feature is not available, this bit is reserved and should be cleared to 0.
		0		Autoflow control is disabled.
		1		Autoflow control is enabled:
				• When RTS = 0, CTS is only enabled.
				• When RTS = 1, RTS and CTS are enabled.

4	LOOP			Loop back mode enable. LOOP is used for the diagnostic testing using the loop back feature.
		0		Loop back mode is disabled.
		1		Loop back mode is enabled. When LOOP is set, the following occur:
				• The UART_TX signal is set high.
				• The UART_RX pin is disconnected
				• The output of the transmitter shift register (TSR) is lopped back in to the receiver shift register (RSR)
				input.

3-2	Reserved	0		Reserved

1	RTS			RTS control. When AFE = 1, the RTS bit determines the autoflow control enabled. Note that all UARTs
				do not support this feature, see the device-specific data manual for supported features. If this feature is
				not available, this bit is reserved and should be cleared to 0.
		0		RTS is disabled, CTS is only enabled.
		1		RTS and CTS are enabled.

0	Reserved	0		Reserved

30	Universal Asynchronous Receiver/Transmitter (UART)	SPRU997C –December 2009
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Copyright © 2009, Texas Instruments Incorporated

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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Features Purpose of the PeripheralFeature Support Functional Block DiagramUart Supported Features/Characteristics by Instance Industry Standards Compliance StatementUart Block Diagram FifoDlhdll Clock Generation and ControlUart BclkBaud Rate Divisor Value Actual Baud Rate Error % Baud Rate Examples for 27 MHz Uart Input ClockStart Parity STOP1 STOP2 Signal Descriptions Pin MultiplexingProtocol Description Parity STOP1 Endianness ConsiderationsData Format ParityOperation Fifo Modes Character Time for Word LengthsCharacter Time Four Character Times Uart Interface Using Autoflow Diagram Autoflow ControlAutoflow Functional Timing Waveforms for RTS Loopback ControlReset Considerations InitializationInterrupt Support Uart Interrupt Request Interrupt Source Enable bitsUart Interrupt Requests Descriptions CommentPower Management DMA Event SupportEmulation Considerations Divisor Latch Not Programmed Changing Operating Mode During Busy Serial CommunicationException Processing Uart RegistersReceiver Buffer Register RBR Field Descriptions Access considerationsReceiver Buffer Register RBR Bit FieldTransmitter Holding Register THR Transmitter Holding Register THR Field DescriptionsBit Field Value Description Elsi Etbei Erbi Interrupt Enable Register IERInterrupt Enable Register IER Field Descriptions ElsiAccess consideration Interrupt Identification Register IIRInterrupt Identification Register IIR Field Descriptions IIR Bits Fifo Control Register FCRInterrupt Identification and Interrupt Clearing Information Interrupt Type Interrupt SourceDMAMODE11 Txclr Rxclr Fifoen Fifo Control Register FCR Field DescriptionsRxfiftl DMAMODE1Dlab EPS PEN STB WLS Line Control Register LCRLine Control Register LCR Field Descriptions DlabST Bit EPS Bit PEN Bit Parity Option Relationship Between ST, EPS, and PEN Bits in LCRNumber of Stop Bits Generated STB BitLoop Modem Control Register MCRModem Control Register MCR Field Descriptions AFELine Status Register LSR Non-FIFO modeFifo mode Line Status Register LSR Field DescriptionsSet Elsi = 1 in IER, an interrupt request is generated Divisor Latches DLL and DLH Register RBRDivisor LSB Latch DLL Field Descriptions Divisor MSB Latch DLH Field DescriptionsCLS Peripheral Identification Registers PID1 and PID2CLS REV TYPFree Power and Emulation Management Register PwremumgmtUtrst Urrst UtrstDocument Revision History Reference Additions/Modifications/DeletionsImportant Notice

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