Texas Instruments TMS320DM643X DMP manual Reset Considerations, Initialization, Interrupt Support

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Peripheral Architecture

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2.7Reset Considerations

2.7.1Software Reset Considerations

Two bits in the power and emulation management register (PWREMU_MGMT) control resetting the parts of the UART:

•The UTRST bit controls resetting the transmitter only. If UTRST = 1, the transmitter is active; if UTRST = 0, the transmitter is in reset.

•The URRST bit controls resetting the receiver only. If URRST = 1, the receiver is active; if URRST = 0, the receiver is in reset.

In each case, putting the receiver and/or transmitter in reset will reset the state machine of the affected portion but does not affect the UART registers.

2.7.2Hardware Reset Considerations

When the processor RESET pin is asserted, the entire processor is reset and is held in the reset state until the RESET pin is released. As part of a device reset, the UART state machine is reset and the UART registers are forced to their default states. The default states of the registers are shown in Section 3.

2.8Initialization

The following steps are required to initialize the UART:

1.Perform the necessary device pin multiplexing setup (see the device-specific data manual).

2.Program the VDD3P3V_PWDN register to power up the IO pins for the UART (see the device-specific data manual).

3.Set the desired baud rate by writing the appropriate clock divisor values to the divisor latch registers (DLL and DLH).

4.If the FIFOs will be used, select the desired trigger level and enable the FIFOs by writing the appropriate values to the FIFO control register (FCR). The FIFOEN bit in FCR must be set first, before the other bits in FCR are configured.

5.Choose the desired protocol settings by writing the appropriate values to the line control register (LCR).

6.If autoflow control is desired, write appropriate values to the modem control register (MCR). Note that all UARTs do not support autoflow control, see the device-specific data manual for supported features.

7.Choose the desired response to emulation suspend events by configuring the FREE bit and enable the UART by setting the UTRST and URRST bits in the power and emulation management register (PWREMU_MGMT).

2.9Interrupt Support

2.9.1Interrupt Events and Requests

The UART generates the interrupt requests described in Table 5. All requests are multiplexed through an arbiter to a single UART interrupt request to the CPU, as shown in Figure 8. Each of the interrupt requests has an enable bit in the interrupt enable register (IER) and is recorded in the interrupt identification register (IIR).

If an interrupt occurs and the corresponding enable bit is set to 1, the interrupt request is recorded in IIR and is forwarded to the CPU. If an interrupt occurs and the corresponding enable bit is cleared to 0, the interrupt request is blocked. The interrupt request is neither recorded in IIR nor forwarded to the CPU.

2.9.2Interrupt Multiplexing

The UARTs have dedicated interrupt signals to the DSP CPU and the interrupts are not multiplexed with any other interrupt source.

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Universal Asynchronous Receiver/Transmitter (UART)

SPRU997C –December 2009

 

 

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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Features Purpose of the PeripheralFeature Support Functional Block DiagramUart Supported Features/Characteristics by Instance Industry Standards Compliance StatementUart Block Diagram FifoDlhdll Clock Generation and ControlUart BclkBaud Rate Divisor Value Actual Baud Rate Error % Baud Rate Examples for 27 MHz Uart Input ClockStart Parity STOP1 STOP2 Signal Descriptions Pin MultiplexingProtocol Description Parity STOP1 Endianness ConsiderationsData Format ParityOperation Fifo Modes Character Time for Word LengthsCharacter Time Four Character Times Uart Interface Using Autoflow Diagram Autoflow ControlAutoflow Functional Timing Waveforms for RTS Loopback ControlReset Considerations InitializationInterrupt Support Uart Interrupt Request Interrupt Source Enable bitsUart Interrupt Requests Descriptions CommentPower Management DMA Event SupportEmulation Considerations Divisor Latch Not Programmed Changing Operating Mode During Busy Serial CommunicationException Processing Uart RegistersReceiver Buffer Register RBR Field Descriptions Access considerationsReceiver Buffer Register RBR Bit FieldTransmitter Holding Register THR Transmitter Holding Register THR Field DescriptionsBit Field Value Description Elsi Etbei Erbi Interrupt Enable Register IERInterrupt Enable Register IER Field Descriptions ElsiAccess consideration Interrupt Identification Register IIRInterrupt Identification Register IIR Field Descriptions IIR Bits Fifo Control Register FCRInterrupt Identification and Interrupt Clearing Information Interrupt Type Interrupt SourceDMAMODE11 Txclr Rxclr Fifoen Fifo Control Register FCR Field DescriptionsRxfiftl DMAMODE1Dlab EPS PEN STB WLS Line Control Register LCRLine Control Register LCR Field Descriptions DlabST Bit EPS Bit PEN Bit Parity Option Relationship Between ST, EPS, and PEN Bits in LCRNumber of Stop Bits Generated STB BitLoop Modem Control Register MCRModem Control Register MCR Field Descriptions AFELine Status Register LSR Non-FIFO modeFifo mode Line Status Register LSR Field DescriptionsSet Elsi = 1 in IER, an interrupt request is generated Divisor Latches DLL and DLH Register RBRDivisor LSB Latch DLL Field Descriptions Divisor MSB Latch DLH Field DescriptionsCLS Peripheral Identification Registers PID1 and PID2CLS REV TYPFree Power and Emulation Management Register PwremumgmtUtrst Urrst UtrstDocument Revision History Reference Additions/Modifications/DeletionsImportant Notice
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