Texas Instruments TMS320DM643X DMP Receiver Buffer Register RBR, Access considerations, Bit Field

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Registers

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3.1Receiver Buffer Register (RBR)

The receiver buffer register (RBR) is shown in Figure 9 and described in Table 7.

The UART receiver section consists of a receiver shift register (RSR) and a receiver buffer register (RBR). When the UART is in the FIFO mode, RBR is a 16-byte FIFO. Timing is supplied by the 16x receiver clock. Receiver section control is a function of the line control register (LCR).

RSR receives serial data from the RX pin. Then RSR concatenates the data and moves it into RBR (or the receiver FIFO). In the non-FIFO mode, when a character is placed in RBR and the receiver data-ready interrupt is enabled (DR = 1 in IER), an interrupt is generated. This interrupt is cleared when the character is read from RBR. In the FIFO mode, the interrupt is generated when the FIFO is filled to the trigger level selected in the FIFO control register (FCR), and it is cleared when the FIFO contents drop below the trigger level.

Access considerations:

RBR, THR, and DLL share one address. To read RBR, write 0 to the DLAB bit in LCR, and read from the shared address. When DLAB = 0, writing to the shared address modifies THR. When DLAB = 1, all accesses at the shared address read or modify DLL.

DLL also has a dedicated address. If you use the dedicated address, you can keep DLAB = 0, so that RBR and THR are always selected at the shared address.

Figure 9. Receiver Buffer Register (RBR)

31				16
	Reserved

		R-0
15	8	7		0

	Reserved			DATA
	R-0			R-0

LEGEND: R = Read only; -n= value after reset

			Table 7. Receiver Buffer Register (RBR) Field Descriptions

Bit	Field	Value	Description

31-8	Reserved	0	Reserved

7-0	DATA	0-FFh	Received data

22	Universal Asynchronous Receiver/Transmitter (UART)	SPRU997C –December 2009
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Copyright © 2009, Texas Instruments Incorporated

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Contents Users Guide Submit Documentation Feedback Revision History Appendix aList of Figures List of Tables Read This First Features Purpose of the PeripheralFeature Support Functional Block DiagramUart Supported Features/Characteristics by Instance Industry Standards Compliance StatementUart Block Diagram FifoDlhdll Clock Generation and ControlUart BclkBaud Rate Examples for 27 MHz Uart Input Clock Baud Rate Divisor Value Actual Baud Rate Error %Start Parity STOP1 STOP2 Pin Multiplexing Signal DescriptionsProtocol Description Parity STOP1 Endianness ConsiderationsData Format ParityOperation Character Time for Word Lengths Fifo ModesCharacter Time Four Character Times Uart Interface Using Autoflow Diagram Autoflow ControlAutoflow Functional Timing Waveforms for RTS Loopback ControlInitialization Reset ConsiderationsInterrupt Support Uart Interrupt Request Interrupt Source Enable bitsUart Interrupt Requests Descriptions CommentDMA Event Support Power ManagementEmulation Considerations Divisor Latch Not Programmed Changing Operating Mode During Busy Serial CommunicationException Processing Uart RegistersReceiver Buffer Register RBR Field Descriptions Access considerationsReceiver Buffer Register RBR Bit FieldTransmitter Holding Register THR Field Descriptions Transmitter Holding Register THRBit Field Value Description Elsi Etbei Erbi Interrupt Enable Register IERInterrupt Enable Register IER Field Descriptions ElsiInterrupt Identification Register IIR Access considerationInterrupt Identification Register IIR Field Descriptions IIR Bits Fifo Control Register FCRInterrupt Identification and Interrupt Clearing Information Interrupt Type Interrupt SourceDMAMODE11 Txclr Rxclr Fifoen Fifo Control Register FCR Field DescriptionsRxfiftl DMAMODE1Dlab EPS PEN STB WLS Line Control Register LCRLine Control Register LCR Field Descriptions DlabST Bit EPS Bit PEN Bit Parity Option Relationship Between ST, EPS, and PEN Bits in LCRNumber of Stop Bits Generated STB BitLoop Modem Control Register MCRModem Control Register MCR Field Descriptions AFELine Status Register LSR Non-FIFO modeFifo mode Line Status Register LSR Field DescriptionsSet Elsi = 1 in IER, an interrupt request is generated Divisor Latches DLL and DLH Register RBRDivisor LSB Latch DLL Field Descriptions Divisor MSB Latch DLH Field DescriptionsCLS Peripheral Identification Registers PID1 and PID2CLS REV TYPFree Power and Emulation Management Register PwremumgmtUtrst Urrst UtrstDocument Revision History Reference Additions/Modifications/DeletionsImportant Notice

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