Texas Instruments TMS320DM643X DMP Uart Interrupt Requests Descriptions, Comment, Conditions

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Peripheral Architecture

Table 5. UART Interrupt Requests Descriptions

UART Interrupt

 

Request

Interrupt Source

 

 

THREINT

THR-empty condition: The transmitter holding register

 

(THR) or the transmitter FIFO is empty. All of the data

 

has been copied from THR to the transmitter shift

 

register (TSR).

RDAINT

Receive data available in non-FIFO mode or trigger

 

level reached in the FIFO mode.

Comment

If THREINT is enabled in IER, by setting the ETBEI bit, it is recorded in IIR.

As an alternative to using THREINT, the CPU can poll the THRE bit in the line status register (LSR).

If RDAINT is enabled in IER, by setting the ERBI bit, it is recorded in IIR.

As an alternative to using RDAINT, the CPU can poll the DR bit in the line status register (LSR). In the FIFO mode, this is not a functionally equivalent alternative because the DR bit does not respond to the FIFO trigger level. The DR bit only indicates the presence or absence of unread characters.

RTOINT

Receiver time-out condition (in the FIFO mode only):

 

No characters have been removed from or input to

 

the receiver FIFO during the last four character times

 

(see Table 4), and there is at least one character in

 

the receiver FIFO during this time.

The receiver time-out interrupt prevents the UART from waiting indefinitely, in the case when the receiver FIFO level is below the trigger level and thus does not generate a receiver data-ready interrupt.

If RTOINT is enabled in IER, by setting the ERBI bit, it is recorded in IIR.

There is no status bit to reflect the occurrence of a time-out condition.

RLSINT

Receiver line status condition: An overrun error, parity

 

error, framing error, or break has occurred.

If RLSINT is enabled in IER, by setting the ELSI bit, it is recorded in IIR.

As an alternative to using RLSINT, the CPU can poll the following bits in the line status register (LSR): overrun error indicator (OE), parity error indicator (PE), framing error indicator (FE), and break indicator (BI).

Figure 8. UART Interrupt Request Enable Paths

Conditions

Transmitter holding register empty

Receiver data ready

Receiver time-out

Overrun error

Parity error

Framing error

Break

Enable bits

UART interrupt requests

THREINT

IER(ETBEI)

RDRINT

IER(ERBI)

RTOINT

RLSINT

IER(ELSI)

Arbiter

UART interrupt request to CPU

SPRU997C –December 2009

Universal Asynchronous Receiver/Transmitter (UART)

19

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Copyright © 2009, Texas Instruments Incorporated

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Contents Users Guide Submit Documentation Feedback Appendix a Revision HistoryList of Figures List of Tables Read This First Purpose of the Peripheral FeaturesIndustry Standards Compliance Statement Functional Block DiagramUart Supported Features/Characteristics by Instance Feature SupportFifo Uart Block DiagramBclk Clock Generation and ControlUart DlhdllBaud Rate Examples for 27 MHz Uart Input Clock Baud Rate Divisor Value Actual Baud Rate Error %Start Parity STOP1 STOP2 Pin Multiplexing Signal DescriptionsProtocol Description Parity Endianness ConsiderationsData Format Parity STOP1Operation Character Time for Word Lengths Fifo ModesCharacter Time Four Character Times Autoflow Control Uart Interface Using Autoflow DiagramLoopback Control Autoflow Functional Timing Waveforms for RTSInitialization Reset ConsiderationsInterrupt Support Comment Enable bitsUart Interrupt Requests Descriptions Uart Interrupt Request Interrupt SourceDMA Event Support Power ManagementEmulation Considerations Uart Registers Changing Operating Mode During Busy Serial CommunicationException Processing Divisor Latch Not ProgrammedBit Field Access considerationsReceiver Buffer Register RBR Receiver Buffer Register RBR Field DescriptionsTransmitter Holding Register THR Field Descriptions Transmitter Holding Register THRBit Field Value Description Elsi Interrupt Enable Register IERInterrupt Enable Register IER Field Descriptions Elsi Etbei ErbiInterrupt Identification Register IIR Access considerationInterrupt Identification Register IIR Field Descriptions Interrupt Type Interrupt Source Fifo Control Register FCRInterrupt Identification and Interrupt Clearing Information IIR BitsDMAMODE1 Fifo Control Register FCR Field DescriptionsRxfiftl DMAMODE11 Txclr Rxclr FifoenDlab Line Control Register LCRLine Control Register LCR Field Descriptions Dlab EPS PEN STB WLSSTB Bit Relationship Between ST, EPS, and PEN Bits in LCRNumber of Stop Bits Generated ST Bit EPS Bit PEN Bit Parity OptionAFE Modem Control Register MCRModem Control Register MCR Field Descriptions LoopLine Status Register LSR Field Descriptions Non-FIFO modeFifo mode Line Status Register LSRSet Elsi = 1 in IER, an interrupt request is generated Register RBR Divisor Latches DLL and DLHDivisor MSB Latch DLH Field Descriptions Divisor LSB Latch DLL Field DescriptionsTYP Peripheral Identification Registers PID1 and PID2CLS REV CLSUtrst Power and Emulation Management Register PwremumgmtUtrst Urrst FreeReference Additions/Modifications/Deletions Document Revision HistoryImportant Notice
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