SMC Networks ARM720T_LH79520, LH79520 SoC ARM720T manual Summary, Features, Available Devices

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The ARM720T macrocell within the physical LH79520 is built around an ARM7TDMI-S core processor. This processor is an implementation of the ARM architecture v4T.

Summary

Core Reference

CR0162 (v2.0) March 10, 2008

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor

This document provides information on Altium Designer's Wishbone wrapper support for the discrete Sharp Bluestreak® LH79520 – a fully integrated 32-bit System-on- Chip (SoC), based on an ARM720T 32-bit RISC processor core.

Altium Designer's ARM720T_LH79520 component is a 32-bit Wishbone-compatible RISC processor.

Although placed in an Altium Designer-based FPGA project just like any other 32-bit processor component, the ARM720T_LH79520 is essentially a Wishbone-compliant wrapper that allows communication with, and use of, the discrete ARM720T processor encapsulated within the Sharp Bluestreak LH79520 device. You can think of the wrapper as being the

'means' by which to facilitate use of external memory and peripheral devices – defined within an FPGA – with the discrete processor.

The ARM720T_LH79520 wrapper can be used in FPGA designs targeting any physical FPGA device – you are not constrained to a particular vendor or platform.

Features

3-stage pipelined RISC processor

4GByte address space

32-bit ARM instruction set

Wishbone I/O and memory ports for simplified peripheral connection

Full Viper-based software development tool chain – C compiler/assembler/source-level debugger/profiler

C-code compatible with other Altium Designer 8-bit and 32-bit Wishbone-compliant processors, for easy design migration.

For further information on ARM720T features, refer to the following documents, available from www.arm.com:

ARM720T Technical Reference Manual

ARM7TDMI-S Technical Reference Manual

Code written for the ARM720T is binary-compatible with other members of the ARM7 family of processors. It is also forward-compatible with ARM9, ARM9E, and ARM10 processor families.

For further information on LH79520 features, refer to the following documents, available from www.sharpsma.com:

LH79520 Product Brief

LH79520 Data Sheet

LH79520 System-on-Chip User's Guide

Available Devices

From a schematic document, the ARM720T_LH79520 device can be found in the FPGA Processors integrated library (FPGA Processors.IntLib), located in the \Library\Fpga folder of the installation.

From an OpenBus System document, the ARM720T_LH79520 component can be found in the Processor Wrappers region of the OpenBus Palette panel.

CR0162 (v2.0) March 10, 2008

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Summary FeaturesAvailable Devices Risc Processor Background Why use Soft Processors?History Soft Fpga ProcessorsWishbone Bus Interfaces ARM720TLH79520Processor Abstraction System Wishbone OpenBUS Processor WrappersDesign Migration Architectural Overview SymbolPin Description Name Type Polarity/Bus size Description Control SignalsPhysical LH79520 Interface Signals Name Type Polarity/Bus size Description Configuring the ProcessorCurrent configuration settings for the processor Defining the Memory Map Memory & I/O ManagementBuilding the Bridge between the Hardware and Software CR0162 v2.0 March 10 Division of Memory Space Configuring the ProcessorDedicated System Interconnect Components Internal Memory Peripheral I/O External MemoryWords, Half-Words and Bytes Data OrganizationPhysical Interface to Memory and Peripherals #define Port32 *volatile unsigned int* Port32Address Hardware Description ResetClocking InterruptsWriting to a Slave Wishbone Peripheral Device Wishbone CommunicationsReading from a Slave Wishbone Peripheral Device Writing to a Slave Wishbone Memory DeviceWishbone Timing Reading from a Slave Wishbone Memory DevicePlacing an ARM720TLH79520 in an Fpga design Design using a Schematic onlyDesign Featuring an OpenBus System Facilitating Communications Downloading Your Design Additional Soft Devices in Your DesignEnabling the Soft Devices Jtag Chain On-Chip Debugging Accessing the Debug EnvironmentStarting an embedded code debug session CR0162 v2.0 March 10 CR0162 v2.0 March 10 Revision History Instruction Set