SMC Networks LH79520 SoC ARM720T, ARM720T_LH79520 manual CR0162 v2.0 March 10

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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor

Figure 17. Workspace panels offering code-specific information and controls

Figure 18. Workspace panels offering information specific to the parent processor.

Full-feature debugging is of course enjoyed at the source code level – from within the source code file itself. To a lesser extent, debugging can also be carried out from a dedicated debug panel for the processor. To access1 this panel, first double-click on the icon representing the physical LH79520 device, in the Hard Devices region of the view. The Instrument Rack – Hard Devices panel will appear, with the ARM720T_LH79520 device added to the rack (Figure 19).

Any 'soft' core processor that you have included in the design will appear, when double-clicked, as an Instrument in the Instrument Rack

–Soft Devices panel (along with any other Nexus-enabled devices).

1The debug panels for each of the debug-enabled processors are standard panels and, as such, can be readily accessed from the View » Workspace Panels » Instruments sub menu, or by clicking on the Instruments button at the bottom of the application window and choosing the required panel – for the processor you wish to debug – from the subsequent pop-up menu.

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CR0162 (v2.0) March 10, 2008

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Contents
Available Devices FeaturesSummary History Why use Soft Processors?Risc Processor Background Soft Fpga ProcessorsARM720TLH79520 Wishbone Bus InterfacesDesign Migration Wishbone OpenBUS Processor WrappersProcessor Abstraction System Symbol Architectural OverviewName Type Polarity/Bus size Description Control Signals Pin DescriptionPhysical LH79520 Interface Signals Configuring the Processor Name Type Polarity/Bus size DescriptionCurrent configuration settings for the processor Building the Bridge between the Hardware and Software Memory & I/O ManagementDefining the Memory Map CR0162 v2.0 March 10 Dedicated System Interconnect Components Configuring the ProcessorDivision of Memory Space Internal Memory External Memory Peripheral I/OPhysical Interface to Memory and Peripherals Data OrganizationWords, Half-Words and Bytes #define Port32 *volatile unsigned int* Port32Address Clocking ResetHardware Description InterruptsReading from a Slave Wishbone Peripheral Device Wishbone CommunicationsWriting to a Slave Wishbone Peripheral Device Writing to a Slave Wishbone Memory DeviceReading from a Slave Wishbone Memory Device Wishbone TimingDesign using a Schematic only Placing an ARM720TLH79520 in an Fpga designDesign Featuring an OpenBus System Facilitating Communications Enabling the Soft Devices Jtag Chain Additional Soft Devices in Your DesignDownloading Your Design Accessing the Debug Environment On-Chip DebuggingStarting an embedded code debug session CR0162 v2.0 March 10 CR0162 v2.0 March 10 Instruction Set Revision History