SMC Networks ARM720T_LH79520, LH79520 SoC ARM720T manual Starting an embedded code debug session

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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor

Figure 16. Starting an embedded code debug session.

The debug environment offers the full suite of tools you would expect to see in order to efficiently debug the embedded code. These features include:

•Setting Breakpoints

•Adding Watches

•Stepping into and over at both the source (*.C) and instruction (*.asm) level

•Reset, Run and Halt code execution

•Run to cursor

All of these and other feature commands can be accessed from the Debug menu or the associated Debug toolbar.

Various workspace panels are accessible in the debug environment, allowing you to view/control code-specific features, such as Breakpoints, Watches and Local variables, as well as information specific to the processor in which the code is running, such as memory spaces and registers.

These panels can be accessed from the View » Workspace Panels » Embedded sub menu, or by clicking on the Embedded button at the bottom of the application window and choosing the required panel from the subsequent pop-up menu.

CR0162 (v2.0) March 10, 2008

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Contents Summary FeaturesAvailable Devices Risc Processor Background Why use Soft Processors?History Soft Fpga ProcessorsWishbone Bus Interfaces ARM720TLH79520Processor Abstraction System Wishbone OpenBUS Processor WrappersDesign Migration Architectural Overview SymbolPin Description Name Type Polarity/Bus size Description Control SignalsPhysical LH79520 Interface Signals Name Type Polarity/Bus size Description Configuring the ProcessorCurrent configuration settings for the processor Defining the Memory Map Memory & I/O ManagementBuilding the Bridge between the Hardware and Software CR0162 v2.0 March 10 Division of Memory Space Configuring the ProcessorDedicated System Interconnect Components Internal Memory Peripheral I/O External MemoryWords, Half-Words and Bytes Data OrganizationPhysical Interface to Memory and Peripherals #define Port32 *volatile unsigned int* Port32Address Hardware Description ResetClocking InterruptsWriting to a Slave Wishbone Peripheral Device Wishbone CommunicationsReading from a Slave Wishbone Peripheral Device Writing to a Slave Wishbone Memory DeviceWishbone Timing Reading from a Slave Wishbone Memory DevicePlacing an ARM720TLH79520 in an Fpga design Design using a Schematic onlyDesign Featuring an OpenBus System Facilitating Communications Downloading Your Design Additional Soft Devices in Your DesignEnabling the Soft Devices Jtag Chain On-Chip Debugging Accessing the Debug EnvironmentStarting an embedded code debug session CR0162 v2.0 March 10 CR0162 v2.0 March 10 Revision History Instruction Set
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