SMC Networks ARM720T_LH79520, LH79520 SoC ARM720T manual Internal Memory

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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor

•cs0 (Bank 0) – 4000_0000h to 43FF_FFFFh

•cs1 (Bank 1) – 4400_0000h to 47FF_FFFFh

•cs2 (Bank 2) – 4800_0000h to 4BFF_FFFFh

•cs3 (Bank 3) – 4C00_0000h to 4FFF_FFFFh

•cs4 (Bank 4) – 5000_0000h to 53FF_FFFFh

•cs5 (Bank 5) – 5400_0000h to 57FF_FFFFh

•cs6 (Bank 6) – 5800_0000h to 5BFF_FFFFh

The bank select signals arrive at the processor's wrapper component in the FPGA on the PER_CS bus.

The block of addresses between 5C00_0000h and 5FFF_FFFFh are RESERVED. Software should not access this range of addresses as doing so will not generate a data abort.

In addition, the lowest bank of external memory – Bank 0 – is mirrored to the lowest page (512MBytes) of the processor's address space, in the range 0000_0000h to 1FFF_FFFFh. This occurs by default after a reset is issued and ensures that exception vectors are correctly placed at addresses 0000_0000h to 0000_001Ch.

Of the seven banks of external memory available, six (cs0-cs5) are used by the ARM720T_LH79520 wrapper when mapping external devices defined in the FPGA.

When configuring the processor's memory from within the FPGA design, the External Static Memory is simplified by dividing it into three regions:

•Peripheral I/O – Bank 5

•External Memory – Banks 1-4

•Internal Memory – Bank 0.

Figure 7 summarizes how these three regions correspond (or are mapped into) the External Static Memory regions of the processor's full address space.

Figure 7. How FPGA-based memory and peripherals map into the physical LH79520's address space.

Internal Memory

The internal "Low" or "Boot" RAM is built using true dual-port FPGA block RAM memory. As such, it can be read or written on both sides, simultaneously, in a single cycle.

This memory still has the standard limitation of load delay slots, because the load from memory happens further down the pipeline, after the Execute stage. As a result, any operation that requires loaded data in the cycle immediately after the load will cause the processor to insert a load stall, holding the first half of the pipeline for one cycle while the data becomes available.

Other than this single limitation, the RAM block is as fast as the internal processor registers themselves.

CR0162 (v2.0) March 10, 2008

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Contents Summary FeaturesAvailable Devices Risc Processor Background Why use Soft Processors?History Soft Fpga ProcessorsWishbone Bus Interfaces ARM720TLH79520Processor Abstraction System Wishbone OpenBUS Processor WrappersDesign Migration Architectural Overview SymbolPin Description Name Type Polarity/Bus size Description Control SignalsPhysical LH79520 Interface Signals Name Type Polarity/Bus size Description Configuring the ProcessorCurrent configuration settings for the processor Defining the Memory Map Memory & I/O ManagementBuilding the Bridge between the Hardware and Software CR0162 v2.0 March 10 Division of Memory Space Configuring the ProcessorDedicated System Interconnect Components Internal Memory Peripheral I/O External MemoryWords, Half-Words and Bytes Data OrganizationPhysical Interface to Memory and Peripherals #define Port32 *volatile unsigned int* Port32Address Hardware Description ResetClocking InterruptsWriting to a Slave Wishbone Peripheral Device Wishbone CommunicationsReading from a Slave Wishbone Peripheral Device Writing to a Slave Wishbone Memory DeviceWishbone Timing Reading from a Slave Wishbone Memory DevicePlacing an ARM720TLH79520 in an Fpga design Design using a Schematic onlyDesign Featuring an OpenBus System Facilitating Communications Downloading Your Design Additional Soft Devices in Your DesignEnabling the Soft Devices Jtag Chain On-Chip Debugging Accessing the Debug EnvironmentStarting an embedded code debug session CR0162 v2.0 March 10 CR0162 v2.0 March 10 Revision History Instruction Set
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