SMC Networks LH79520 SoC ARM720T manual On-Chip Debugging, Accessing the Debug Environment

Page 24

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor

•Download of the embedded code targeted to the discrete ARM720T device. Click on the LH79520 device in the Hard Devices chain to access the process flow required to download the embedded software to the processor, as illustrated below. Notice that the process flow consist of compilation and download only.

On-Chip Debugging

To facilitate real-time debugging of the processor, the ARM720T_LH79520 includes On-Chip Debug hardware that can be accessed using the standard JTAG interface.

With this hardware, the following set of additional functional features are provided:

•Reset, Go, Halt processor control

•Single or multi-step debugging

•Read-write access for internal processor registers

•Read-write access for memory and I/O space

•Unlimited software breakpoints.

Accessing the Debug Environment

Debugging of the embedded code within an ARM720T_LH79520 processor is carried out by starting a debug session. Prior to starting the session, you must ensure that the FPGA design has been downloaded to the target FPGA device and the embedded code has been downloaded to the physical ARM720T device (see Downloading your design).

To start a debug session for the embedded code running in the ARM720T_LH79520, simply right- click on the icon for the physical device in the Hard Devices region of the Devices view, and choose the Debug command from the pop-up menu that appears.

The embedded project for the software running in the processor will initially be recompiled and the debug session will commence. The relevant source code document (either Assembly or C) will be opened and the current execution point will be set to the first line of executable code (see Figure 16).

You can have multiple debug sessions running simultaneously

–one per embedded software project associated with a processor in the design.

To start a debug session for the embedded code running in a 'soft' processor in the design, simply right-click on the icon for that processor, in the Soft Devices region of the view, and choose the Debug command from the menu.

24

CR0162 (v2.0) March 10, 2008

Page 23 Page 25
Image 24
Page 23 Page 25
Contents
Features SummaryAvailable Devices Why use Soft Processors? Risc Processor BackgroundHistory Soft Fpga ProcessorsARM720TLH79520 Wishbone Bus InterfacesWishbone OpenBUS Processor Wrappers Processor Abstraction SystemDesign Migration Symbol Architectural OverviewName Type Polarity/Bus size Description Control Signals Pin DescriptionPhysical LH79520 Interface Signals Configuring the Processor Name Type Polarity/Bus size DescriptionCurrent configuration settings for the processor Memory & I/O Management Defining the Memory MapBuilding the Bridge between the Hardware and Software CR0162 v2.0 March 10 Configuring the Processor Division of Memory SpaceDedicated System Interconnect Components Internal Memory External Memory Peripheral I/OData Organization Words, Half-Words and BytesPhysical Interface to Memory and Peripherals #define Port32 *volatile unsigned int* Port32Address Reset Hardware DescriptionClocking InterruptsWishbone Communications Writing to a Slave Wishbone Peripheral DeviceReading from a Slave Wishbone Peripheral Device Writing to a Slave Wishbone Memory DeviceReading from a Slave Wishbone Memory Device Wishbone TimingDesign using a Schematic only Placing an ARM720TLH79520 in an Fpga designDesign Featuring an OpenBus System Facilitating Communications Additional Soft Devices in Your Design Downloading Your DesignEnabling the Soft Devices Jtag Chain Accessing the Debug Environment On-Chip DebuggingStarting an embedded code debug session CR0162 v2.0 March 10 CR0162 v2.0 March 10 Instruction Set Revision History