SMC Networks ARM720T_LH79520, LH79520 SoC ARM720T manual Design Featuring an OpenBus System

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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor

Design Featuring an OpenBus System

Figure 11 illustrates identical use of the ARM720T_LH79520 within a design where the main processor system has been defined as an OpenBus System. Peripherals (and memory) are connected to the processor through an Interconnect component. The OpenBus System environment is a much more abstract and intuitive place to create a design, where the interfaces are reduced to single ports and connection is made courtesy of single links.

Figure 11. Wiring up the ARM720T_LH79520 wrapper as part of an OpenBus System.

Much of the configuration is handled for you, with each peripheral added as a slave to the Interconnect component by virtue of its link. The Interconnect contains information regarding each peripheral's address bus size and a default decoder address width. All that is really needed is specification of the base address for each peripheral – where in the ARM720T_LH79520's address space these devices are to be mapped.

An OpenBus System is defined on an OpenBus System Document (*.OpenBus). This document is referenced from the FPGA design's top-level schematic sheet through a sheet symbol. Figure 12 illustrates the interface circuitry between the ARM720T_LH79520's physical processor interface and the physical pins of the target FPGA device – represented by the PROCESSOR_ARM7_LH79520 port component.

CR0162 (v2.0) March 10, 2008

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Contents Features SummaryAvailable Devices Risc Processor Background Why use Soft Processors?History Soft Fpga ProcessorsWishbone Bus Interfaces ARM720TLH79520Wishbone OpenBUS Processor Wrappers Processor Abstraction SystemDesign Migration Architectural Overview SymbolPin Description Name Type Polarity/Bus size Description Control SignalsPhysical LH79520 Interface Signals Name Type Polarity/Bus size Description Configuring the ProcessorCurrent configuration settings for the processor Memory & I/O Management Defining the Memory MapBuilding the Bridge between the Hardware and Software CR0162 v2.0 March 10 Configuring the Processor Division of Memory SpaceDedicated System Interconnect Components Internal Memory Peripheral I/O External MemoryData Organization Words, Half-Words and BytesPhysical Interface to Memory and Peripherals #define Port32 *volatile unsigned int* Port32Address Hardware Description ResetClocking InterruptsWriting to a Slave Wishbone Peripheral Device Wishbone CommunicationsReading from a Slave Wishbone Peripheral Device Writing to a Slave Wishbone Memory DeviceWishbone Timing Reading from a Slave Wishbone Memory DevicePlacing an ARM720TLH79520 in an Fpga design Design using a Schematic onlyDesign Featuring an OpenBus System Facilitating Communications Additional Soft Devices in Your Design Downloading Your DesignEnabling the Soft Devices Jtag Chain On-Chip Debugging Accessing the Debug EnvironmentStarting an embedded code debug session CR0162 v2.0 March 10 CR0162 v2.0 March 10 Revision History Instruction Set
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