SMC Networks LH79520 SoC ARM720T manual Wishbone OpenBUS Processor Wrappers, Design Migration

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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor

Wishbone OpenBUS Processor Wrappers

To normalize access to hardware and peripherals, each of the 32-bit processors supported in Altium Designer has a Wishbone OpenBUS-based FPGA core that 'wraps' around the processor. This enables peripherals defined in the FPGA to be used transparently with any type of processor. An FPGA OpenBUS wrapper around discrete, hard-wired peripherals also allows them to be moved seamlessly between processors.

The OpenBUS wrappers can be implemented in any FPGA and allow the designer to implement FPGA-based portable cores, taking advantage of the device driver system in Altium Designer for both FPGA-based soft-core peripherals as well as connections to off-chip discrete peripherals and memory devices.

Processor Abstraction System

Use of OpenBUS wrappers creates a plug-in processor abstraction system that normalizes the interface to interrupt systems and other hardware specific elements. The system provides an identical interface to the processor's interrupt system, whether soft or hard-vectored. This allows different processors to be used transparently with identical source code bases.

Design Migration

With each 32-bit processor encased in a Wishbone OpenBUS wrapper, an embedded software design can be seamlessly moved between soft-core processors, hybrid hard-core processors and discrete processors.

The Wishbone OpenBUS wrapper around the ARM720T_LH79520 processor makes it architecturally similar to the other 32-bit processors included with Altium Designer, both in terms of its memory map and its pinout. This allows for easy migration from the ARM720T_LH79520 to any of the following devices:

TSK3000A 32-bit RISC processor, device and vendor-independent. (Refer to the TSK3000A 32-bit RISC Processor core reference).

PPC405A – 'hard' PowerPC® 32-bit RISC processor immersed on the Xilinx Virtex-II Pro. (Refer to the PPC405A 32-bit RISC Processor core reference).

MicroBlaze32-bit RISC processor targeted to Xilinx FPGA platforms. (Refer to the MicroBlaze 32-bit RISC Processor core reference).

Nios® II 32-bit RISC processor targeted to Altera FPGA platforms. (Refer to the Nios II 32-bit RISC Processor core reference).

CoreMP7 32-bit RISC processor targeted to Actel FPGA platforms.

PPC405CR – AMCC® PowerPC 32-bit RISC processor. (Refer to the PPC405CR - AMCC PowerPC 32-bit RISC Processor core reference).

Altium Designer also features Wishbone-compliant versions of its TSK52x 8-bit processor. These Wishbone variants, along with true C-code compatibility between these and the ARM720T_LH79520, allow designs to be easily moved between the 8- and 32- bit worlds.

For further information on the TSK52x, refer to the TSK52x MCU core reference.

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CR0162 (v2.0) March 10, 2008

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Contents Summary FeaturesAvailable Devices Why use Soft Processors? Risc Processor BackgroundHistory Soft Fpga ProcessorsARM720TLH79520 Wishbone Bus InterfacesProcessor Abstraction System Wishbone OpenBUS Processor WrappersDesign Migration Symbol Architectural OverviewName Type Polarity/Bus size Description Control Signals Pin DescriptionPhysical LH79520 Interface Signals Configuring the Processor Name Type Polarity/Bus size DescriptionCurrent configuration settings for the processor Defining the Memory Map Memory & I/O ManagementBuilding the Bridge between the Hardware and Software CR0162 v2.0 March 10 Division of Memory Space Configuring the ProcessorDedicated System Interconnect Components Internal Memory External Memory Peripheral I/OWords, Half-Words and Bytes Data OrganizationPhysical Interface to Memory and Peripherals #define Port32 *volatile unsigned int* Port32Address Reset Hardware DescriptionClocking InterruptsWishbone Communications Writing to a Slave Wishbone Peripheral DeviceReading from a Slave Wishbone Peripheral Device Writing to a Slave Wishbone Memory DeviceReading from a Slave Wishbone Memory Device Wishbone TimingDesign using a Schematic only Placing an ARM720TLH79520 in an Fpga designDesign Featuring an OpenBus System Facilitating Communications Downloading Your Design Additional Soft Devices in Your DesignEnabling the Soft Devices Jtag Chain Accessing the Debug Environment On-Chip DebuggingStarting an embedded code debug session CR0162 v2.0 March 10 CR0162 v2.0 March 10 Instruction Set Revision History