SMC Networks ARM720T_LH79520, LH79520 SoC ARM720T manual CR0162 v2.0 March 10

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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor

Figure 19. Accessing debug features from the processor's instrument panel

The Nexus Debugger button provides access to the associated debug panel (Figure 20), which in turn allows you to interrogate and to a lighter extent control, debugging of the processor and its embedded code, notably with respect to the registers and memory.

One key feature of the debug panel is that it enables you to specify (and therefore change) the embedded code (HEX file) that is downloaded to the processor, quickly and efficiently.

Figure 20. Processor debugging using the associated processor debug panel.

For more information on the content and use of processor debug panels, press F1 when the cursor is over one of these panels.

For further information regarding the use of the embedded tools for the ARM720T_LH79520, see the Using the ARM Embedded Tools guide.

For comprehensive information with respect to the embedded tools available for the ARM720T_LH79520, see the ARM Embedded Tools Reference.

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Contents Features SummaryAvailable Devices Soft Fpga Processors Why use Soft Processors?Risc Processor Background HistoryWishbone Bus Interfaces ARM720TLH79520Wishbone OpenBUS Processor Wrappers Processor Abstraction SystemDesign Migration Architectural Overview SymbolPin Description Name Type Polarity/Bus size Description Control SignalsPhysical LH79520 Interface Signals Name Type Polarity/Bus size Description Configuring the ProcessorCurrent configuration settings for the processor Memory & I/O Management Defining the Memory MapBuilding the Bridge between the Hardware and Software CR0162 v2.0 March 10 Configuring the Processor Division of Memory SpaceDedicated System Interconnect Components Internal Memory Peripheral I/O External MemoryData Organization Words, Half-Words and BytesPhysical Interface to Memory and Peripherals #define Port32 *volatile unsigned int* Port32Address Interrupts ResetHardware Description ClockingWriting to a Slave Wishbone Memory Device Wishbone CommunicationsWriting to a Slave Wishbone Peripheral Device Reading from a Slave Wishbone Peripheral DeviceWishbone Timing Reading from a Slave Wishbone Memory DevicePlacing an ARM720TLH79520 in an Fpga design Design using a Schematic onlyDesign Featuring an OpenBus System Facilitating Communications Additional Soft Devices in Your Design Downloading Your DesignEnabling the Soft Devices Jtag Chain On-Chip Debugging Accessing the Debug EnvironmentStarting an embedded code debug session CR0162 v2.0 March 10 CR0162 v2.0 March 10 Revision History Instruction Set
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