SMC Networks LH79520 SoC ARM720T manual Memory & I/O Management, Defining the Memory Map

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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor

Memory & I/O Management

The ARM720T_LH79520 uses 32-bit address buses providing a 4GByte linear address space. All memory access is in 32-bit words, which creates a physical address bus of 30-bits.

Memory space is broken into seven main areas, as illustrated in Figure 4. Memory and peripheral I/O devices placed and wired within the FPGA design are mapped into the External Static Memory regions of this space. Further information can be found in the section – Division of Memory Space.

Before detailing the mapping of memory and peripheral devices into the processor's address space, it is worthwhile discussing the difficulties involved in this mapping, and the solution that Altium Designer brings to the problem.

Defining the Memory Map

An area that can be difficult to manage in an embedded software development project is the mapping of memory and peripherals into the processor’s address space.

The memory map, as it is often called, is essentially the bridge between the hardware and software projects – the hardware team allocating each of the various memory and peripheral devices their own chunk of the processor’s address space, the software team then writing their code to access the memory and peripherals at the given locations.

To help manage the process of allocating devices into the space there are a number of features available to both the hardware designer and the embedded software developer in Altium Designer.

This discussion is based around the ARM720T_LH79520 processor, however the overall approach can be applied to any of the 32-bit processors available in Altium Designer.

Building the Bridge between the Hardware and Software

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Advanced High-Performance Bus

Peripherals

Advanced Peripheral Bus

Peripherals

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Internal Static Memory

External Static Memory

SDRAM

External Static Memory

Defining the memory map on the hardware (FPGA project) side is essentially a 3 stage process:

•Place the peripheral or memory

Figure 4. Memory organization in the ARM720T_LH79520.

•Define its addressing requirements (this is most easily done using a Wishbone Interconnect device)

•Bring that definition into the processor’s configuration, which can then be accessed by the embedded tools

Figures 5 and 6 show examples of memory and peripheral devices mapped into the addressable memory and IO ranges for the ARM720T_LH79520 respectively.

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CR0162 (v2.0) March 10, 2008

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Contents
Summary FeaturesAvailable Devices History Why use Soft Processors?Risc Processor Background Soft Fpga ProcessorsARM720TLH79520 Wishbone Bus InterfacesProcessor Abstraction System Wishbone OpenBUS Processor WrappersDesign Migration Symbol Architectural OverviewName Type Polarity/Bus size Description Control Signals Pin DescriptionPhysical LH79520 Interface Signals Configuring the Processor Name Type Polarity/Bus size DescriptionCurrent configuration settings for the processor Defining the Memory Map Memory & I/O ManagementBuilding the Bridge between the Hardware and Software CR0162 v2.0 March 10 Division of Memory Space Configuring the ProcessorDedicated System Interconnect Components Internal Memory External Memory Peripheral I/OWords, Half-Words and Bytes Data OrganizationPhysical Interface to Memory and Peripherals #define Port32 *volatile unsigned int* Port32Address Clocking ResetHardware Description InterruptsReading from a Slave Wishbone Peripheral Device Wishbone CommunicationsWriting to a Slave Wishbone Peripheral Device Writing to a Slave Wishbone Memory DeviceReading from a Slave Wishbone Memory Device Wishbone TimingDesign using a Schematic only Placing an ARM720TLH79520 in an Fpga designDesign Featuring an OpenBus System Facilitating Communications Downloading Your Design Additional Soft Devices in Your DesignEnabling the Soft Devices Jtag Chain Accessing the Debug Environment On-Chip DebuggingStarting an embedded code debug session CR0162 v2.0 March 10 CR0162 v2.0 March 10 Instruction Set Revision History