SMC Networks ARM720T_LH79520 Additional Soft Devices in Your Design, Downloading Your Design

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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor

As the physical ARM720T processor does not reside within an FPGA, communications between the host computer and the ARM720T are carried out through the Hard Devices JTAG chain. This is a departure from the normal way of communicating with FPGA-based, debug-enabled devices, such as the 'soft' processors and virtual instruments, whereby communication is carried out through the Soft Devices JTAG chain, and in accordance with the Nexus 5001 standard.

For further information on the JTAG communications, refer to the article AR0130 PC to NanoBoard Communications.

Additional 'Soft' Devices in Your Design

If your design incorporates FPGA-based 'soft' processors and virtual instruments, in addition to the discrete ARM720T processor, these devices will appear in the Soft Devices chain of the Devices view. The Soft Devices chain is determined when the design has been implemented within the target FPGA device. It is not a physical chain, in the sense that you can see no external wiring – the connections required between the Nexus-enabled devices are made internal to the FPGA itself. Figure 14 shows an example of devices presented in this chain.

Figure 14. Nexus-enabled processor (TSK3000A) and virtual instruments appearing in the Soft Devices chain.

Enabling the Soft Devices JTAG Chain

In order to communicate with soft devices in a design (processors and/or virtual instruments) you must enable the Soft Devices JTAG chain within the design. This is done by placing a JTAG Port (NEXUS_JTAG_CONNECTOR) and corresponding Soft Nexus- Chain Connector (NEXUS_JTAG_PORT) on the top schematic sheet of the design, as shown in Figure 15.

If your design incorporates just the discrete ARM720T_LH79520, with no additional 'soft' devices, then these Nexus JTAG devices are not required.

Figure 15. Implementing the soft devices chain within the design.

These devices can be found in the FPGA NB2DSK01 Port-Plugin (FPGA NB2DSK01 Port-Plugin.IntLib) and FPGA Generic (FPGA Generic.IntLib) integrated libraries respectively, both of which are located in the \Library\Fpga folder of the installation.

Downloading Your Design

Download of a design which incorporates a discrete processor such as the ARM720T_LH79520 is performed in two stages:

Download of the FPGA design to the target physical FPGA device. This includes downloading the respective embedded code to any 'soft' processors used within the design. Click on the FPGA device in the Hard Devices chain to access the process flow required to facilitate this part of the download, as illustrated in the following image. The standard process flow is followed when programming the FPGA device – Compile, Synthesize, Build and Program.

CR0162 (v2.0) March 10, 2008

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Contents Available Devices FeaturesSummary Soft Fpga Processors Why use Soft Processors?Risc Processor Background HistoryWishbone Bus Interfaces ARM720TLH79520Design Migration Wishbone OpenBUS Processor WrappersProcessor Abstraction System Architectural Overview SymbolPin Description Name Type Polarity/Bus size Description Control SignalsPhysical LH79520 Interface Signals Name Type Polarity/Bus size Description Configuring the ProcessorCurrent configuration settings for the processor Building the Bridge between the Hardware and Software Memory & I/O ManagementDefining the Memory Map CR0162 v2.0 March 10 Dedicated System Interconnect Components Configuring the ProcessorDivision of Memory Space Internal Memory Peripheral I/O External MemoryPhysical Interface to Memory and Peripherals Data OrganizationWords, Half-Words and Bytes #define Port32 *volatile unsigned int* Port32Address Interrupts ResetHardware Description ClockingWriting to a Slave Wishbone Memory Device Wishbone CommunicationsWriting to a Slave Wishbone Peripheral Device Reading from a Slave Wishbone Peripheral DeviceWishbone Timing Reading from a Slave Wishbone Memory DevicePlacing an ARM720TLH79520 in an Fpga design Design using a Schematic onlyDesign Featuring an OpenBus System Facilitating Communications Enabling the Soft Devices Jtag Chain Additional Soft Devices in Your DesignDownloading Your Design On-Chip Debugging Accessing the Debug EnvironmentStarting an embedded code debug session CR0162 v2.0 March 10 CR0162 v2.0 March 10 Revision History Instruction Set