ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T
As the physical ARM720T processor does not reside within an FPGA, communications between the host computer and the ARM720T are carried out through the Hard Devices JTAG chain. This is a departure from the normal way of communicating with
For further information on the JTAG communications, refer to the article AR0130 PC to NanoBoard Communications.
Additional 'Soft' Devices in Your Design
If your design incorporates
Figure 14. Nexus-enabled processor (TSK3000A) and virtual instruments appearing in the Soft Devices chain.
Enabling the Soft Devices JTAG Chain
In order to communicate with soft devices in a design (processors and/or virtual instruments) you must enable the Soft Devices JTAG chain within the design. This is done by placing a JTAG Port (NEXUS_JTAG_CONNECTOR) and corresponding Soft Nexus- Chain Connector (NEXUS_JTAG_PORT) on the top schematic sheet of the design, as shown in Figure 15.
If your design incorporates just the discrete ARM720T_LH79520, with no additional 'soft' devices, then these Nexus JTAG devices are not required.
Figure 15. Implementing the soft devices chain within the design.
These devices can be found in the FPGA NB2DSK01
Downloading Your Design
Download of a design which incorporates a discrete processor such as the ARM720T_LH79520 is performed in two stages:
•Download of the FPGA design to the target physical FPGA device. This includes downloading the respective embedded code to any 'soft' processors used within the design. Click on the FPGA device in the Hard Devices chain to access the process flow required to facilitate this part of the download, as illustrated in the following image. The standard process flow is followed when programming the FPGA device – Compile, Synthesize, Build and Program.
CR0162 (v2.0) March 10, 2008 | 23 |