SMC Networks LH79520 SoC ARM720T, ARM720T_LH79520 Placing an ARM720TLH79520 in an Fpga design

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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor

Placing an ARM720T_LH79520 in an FPGA design

How the ARM720T_LH79520 is placed and wired within an FPGA design depends on the method used to build that design. The main processor-based system can be defined purely on the schematic sheet, or it can be contained as a separate OpenBus System, which is then referenced from the top-level schematic. The following sections take a look at using the processor in both of these design arenas.

Design using a Schematic only

The partial circuit of Figure 10 shows an example of how an ARM720T_LH79520 is used within a schematic-based FPGA design, making peripheral devices and memory (not shown) available to the physical processor.

Figure 10. Wiring up the ARM720T_LH79520 wrapper in a schematic-based FPGA design.

Memory and peripheral I/O devices are wired to the wrapper's Wishbone External Memory and Peripheral I/O interfaces in the same way as for any other 32-bit processor.

The signals in the wrapper's external interface – the interface to the physical processor itself – must be wired to ports that are mapped accordingly to the required pins of the physical FPGA device in which the FPGA design will be programmed. You must ensure that the relevant signals from the discrete processor device are wired to these FPGA device pins.

20	CR0162 (v2.0) March 10, 2008

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Contents Available Devices FeaturesSummary Why use Soft Processors? Risc Processor BackgroundHistory Soft Fpga ProcessorsARM720TLH79520 Wishbone Bus InterfacesDesign Migration Wishbone OpenBUS Processor WrappersProcessor Abstraction System Symbol Architectural OverviewName Type Polarity/Bus size Description Control Signals Pin DescriptionPhysical LH79520 Interface Signals Configuring the Processor Name Type Polarity/Bus size DescriptionCurrent configuration settings for the processor Building the Bridge between the Hardware and Software Memory & I/O ManagementDefining the Memory Map CR0162 v2.0 March 10 Dedicated System Interconnect Components Configuring the ProcessorDivision of Memory Space Internal Memory External Memory Peripheral I/OPhysical Interface to Memory and Peripherals Data OrganizationWords, Half-Words and Bytes #define Port32 *volatile unsigned int* Port32Address Reset Hardware DescriptionClocking InterruptsWishbone Communications Writing to a Slave Wishbone Peripheral DeviceReading from a Slave Wishbone Peripheral Device Writing to a Slave Wishbone Memory DeviceReading from a Slave Wishbone Memory Device Wishbone TimingDesign using a Schematic only Placing an ARM720TLH79520 in an Fpga designDesign Featuring an OpenBus System Facilitating Communications Enabling the Soft Devices Jtag Chain Additional Soft Devices in Your DesignDownloading Your Design Accessing the Debug Environment On-Chip DebuggingStarting an embedded code debug session CR0162 v2.0 March 10 CR0162 v2.0 March 10 Instruction Set Revision History