SMC Networks ARM720T_LH79520, LH79520 SoC ARM720T manual CR0162 v2.0 March 10

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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor

Figure 5. Memory devices mapped into banks 0- 4 (cs0-cs4) of the ARM720T_LH79520's addressable External Static Memory.

Figure 6. Peripheral devices mapped into bank 5 (cs5) of the ARM720T_LH79520's addressable External Static Memory.

CR0162 (v2.0) March 10, 2008

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Contents Available Devices FeaturesSummary Soft Fpga Processors Why use Soft Processors?Risc Processor Background HistoryWishbone Bus Interfaces ARM720TLH79520Design Migration Wishbone OpenBUS Processor WrappersProcessor Abstraction System Architectural Overview SymbolPin Description Name Type Polarity/Bus size Description Control SignalsPhysical LH79520 Interface Signals Name Type Polarity/Bus size Description Configuring the ProcessorCurrent configuration settings for the processor Building the Bridge between the Hardware and Software Memory & I/O ManagementDefining the Memory Map CR0162 v2.0 March 10 Dedicated System Interconnect Components Configuring the ProcessorDivision of Memory Space Internal Memory Peripheral I/O External MemoryPhysical Interface to Memory and Peripherals Data OrganizationWords, Half-Words and Bytes #define Port32 *volatile unsigned int* Port32Address Interrupts ResetHardware Description ClockingWriting to a Slave Wishbone Memory Device Wishbone CommunicationsWriting to a Slave Wishbone Peripheral Device Reading from a Slave Wishbone Peripheral DeviceWishbone Timing Reading from a Slave Wishbone Memory DevicePlacing an ARM720TLH79520 in an Fpga design Design using a Schematic onlyDesign Featuring an OpenBus System Facilitating Communications Enabling the Soft Devices Jtag Chain Additional Soft Devices in Your DesignDownloading Your Design On-Chip Debugging Accessing the Debug EnvironmentStarting an embedded code debug session CR0162 v2.0 March 10 CR0162 v2.0 March 10 Revision History Instruction Set