SMC Networks ARM720T_LH79520 manual Hardware Description, Clocking, Reset, Interrupts

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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor

Hardware Description

For detailed information about the hardware and functionality of the ARM720T_LH79520 processor, including internal registers, refer to the following reference guide, available from the ARM website:

•ARM720T Technical Reference Manual

Clocking

The signal ARM7_SYS_CLK sent from the processor wrapper to the physical processor itself is simply the internally-routed CLK_I signal. On the physical device side, the ARM7_SYS_CLK signal (arriving as CLKIN) is fed into a PLL. The physical device generates the CLKOUT signal, which is then sent back into the FPGA (arriving at the wrapper as PER_CLK ), where it is used to correctly clock signals to/from the wrapper.

ARM7_SYS_CLK – and therefore CLK_I – must be 100MHz, in order for the PLL to achieve stable locking.

Reset

The signal ARM7_SYS_RESET sent from the processor wrapper to the physical processor itself (arriving as nRESETIN) is simply the internally-routed RST_I signal. A system reset of the FPGA can therefore also be used to reset the physical processor as well.

Conversely, the physical processor can issue a reset of the system, the required signal of which (nRESETOUT) is passed into the FPGA, ultimately arriving at the wrapper on the PER_RESET line.

Interrupts

Although the ARM720T_LH79520 wrapper has provision for 32 interrupt lines, the physical LH79520 device supports only 8 external interrupts. Of these, we use only 5. The least significant 5 lines of the INT_I bus are connected through to the PER_INT bus.

These external interrupts are handled by a Vectored Interrupt Controller (VIC) – part of the physical LH79520 device, but external to the ARM720T processor itself. They appear as interrupts 0 to 4. The Interrupt Controller combines these signals into a single signal sent to the processor's Noncritical interrupt input.

Interrupts generated by Altium Designer Wishbone peripherals have positive polarity and are level sensitive. You will need to

load the least significant 10 bits of the LH79520's Interrupt Configuration Register (IntConfig) with 0101010101 to ensure that these signals are set to trigger on a High level.

The pins to which these external interrupts enter the LH79520 device are multiplexed. Depending on the configuration of the pins, they are either set for use as external interrupts or for some other usage. After a reset, the pins associated with external interrupts 3 and 4 are, by default, configured to be used as interrupts. However, the pins associated with interrupts 0-2 require to be configured as such. This is done by setting bits 2-4 of the LH79520's Miscellaneous Pin Multiplexing Register (MiscMux) High.

Detailed information on the operation of the LH79520's Interrupt Controller can be found in the Exceptions and Interrupts section of the LH79520 System-on-Chip User's Guide. For information on pin configuration, refer to the section I/O Control and Multiplexing.

CR0162 (v2.0) March 10, 2008

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Contents Available Devices FeaturesSummary Risc Processor Background Why use Soft Processors?History Soft Fpga ProcessorsWishbone Bus Interfaces ARM720TLH79520Design Migration Wishbone OpenBUS Processor WrappersProcessor Abstraction System Architectural Overview SymbolPin Description Name Type Polarity/Bus size Description Control SignalsPhysical LH79520 Interface Signals Name Type Polarity/Bus size Description Configuring the ProcessorCurrent configuration settings for the processor Building the Bridge between the Hardware and Software Memory & I/O ManagementDefining the Memory Map CR0162 v2.0 March 10 Dedicated System Interconnect Components Configuring the ProcessorDivision of Memory Space Internal Memory Peripheral I/O External MemoryPhysical Interface to Memory and Peripherals Data OrganizationWords, Half-Words and Bytes #define Port32 *volatile unsigned int* Port32Address Hardware Description ResetClocking InterruptsWriting to a Slave Wishbone Peripheral Device Wishbone CommunicationsReading from a Slave Wishbone Peripheral Device Writing to a Slave Wishbone Memory DeviceWishbone Timing Reading from a Slave Wishbone Memory DevicePlacing an ARM720TLH79520 in an Fpga design Design using a Schematic onlyDesign Featuring an OpenBus System Facilitating Communications Enabling the Soft Devices Jtag Chain Additional Soft Devices in Your DesignDownloading Your Design On-Chip Debugging Accessing the Debug EnvironmentStarting an embedded code debug session CR0162 v2.0 March 10 CR0162 v2.0 March 10 Revision History Instruction Set
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