SMC Networks ARM720T_LH79520, LH79520 SoC ARM720T manual Architectural Overview, Symbol

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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor

Architectural Overview

Symbol

Figure 1. Symbols used for the ARM720T_LH79520 in both schematic (left) and OpenBus System (right).

As can be seen from the schematic symbol in Figure 1, the ARM720T_LH79520 wrapper that is placed in an FPGA design essentially has three interfaces. The Wishbone External Memory and Peripheral I/O interfaces are identical to those of all other 32-bit processors supported by Altium Designer.

The third interface provides connection to the physical LH79520 itself. More specifically, it caters for:

•Data and Address bus signals to/from the LH79520's External Bus Interface (EBI)

•Control signals from the LH79520's Static Memory Controller (SMC)

•Clock, Reset and Interrupt signals.

The corresponding signals from the physical LH79520 must be hardwired to the desired pins of the physical FPGA device. To wire from the ARM720T_LH79520 Wishbone wrapper to the physical pins of the FPGA device requires the use of the relevant port-plugin component (PROCESSOR_ARM7_LH79520). For more information, refer to the section Placing an ARM720T_LH79520 in an FPGA design.

CR0162 (v2.0) March 10, 2008

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Contents
Available Devices FeaturesSummary Risc Processor Background Why use Soft Processors?History Soft Fpga ProcessorsWishbone Bus Interfaces ARM720TLH79520Design Migration Wishbone OpenBUS Processor WrappersProcessor Abstraction System Architectural Overview SymbolPin Description Name Type Polarity/Bus size Description Control SignalsPhysical LH79520 Interface Signals Name Type Polarity/Bus size Description Configuring the ProcessorCurrent configuration settings for the processor Building the Bridge between the Hardware and Software Memory & I/O ManagementDefining the Memory Map CR0162 v2.0 March 10 Dedicated System Interconnect Components Configuring the ProcessorDivision of Memory Space Internal Memory Peripheral I/O External MemoryPhysical Interface to Memory and Peripherals Data OrganizationWords, Half-Words and Bytes #define Port32 *volatile unsigned int* Port32Address Hardware Description ResetClocking InterruptsWriting to a Slave Wishbone Peripheral Device Wishbone CommunicationsReading from a Slave Wishbone Peripheral Device Writing to a Slave Wishbone Memory DeviceWishbone Timing Reading from a Slave Wishbone Memory DevicePlacing an ARM720TLH79520 in an Fpga design Design using a Schematic onlyDesign Featuring an OpenBus System Facilitating Communications Enabling the Soft Devices Jtag Chain Additional Soft Devices in Your DesignDownloading Your Design On-Chip Debugging Accessing the Debug EnvironmentStarting an embedded code debug session CR0162 v2.0 March 10 CR0162 v2.0 March 10 Revision History Instruction Set