SMC Networks ARM720T_LH79520, LH79520 SoC ARM720T manual ARM720TLH79520, Wishbone Bus Interfaces

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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor

Improving and Extending Product Life-Cycles

Fast time to market is usually synonymous with a weaker feature set – a traditional trade-off. With FPGA-based system designs you can have the best of both worlds. You can get your product to market quickly with a limited feature set, then follow-up with more extensive features over time, upgrading the product while it is already in the field.

This not only extends product life-cycles but also lowers the risk of entry, allowing new protocols to be added dynamically and hardware bugs to be fixed without product RMA.

Creating Application-Specific Coprocessors

Algorithms can easily be moved between hardware and software implementations. This allows the design to be initially implemented in software, later off-loading intensive tasks into dedicated hardware, in order to meet performance objectives. Again, this can happen even after commitment to the board-level design.

Implementing Multiple Processors within a Single Device

Extra processors can be added within a single FPGA device, simply by modifying the design with which the device is programmed. Once again, this can be achieved after the board-level design has been finalized and a commitment to production made.

Lowering System Cost

Processors, peripherals, memory and I/O interfaces can be integrated into a single FPGA device, greatly reducing system complexity and cost. Once the FPGA-based embedded application moves to 32-bit, cost becomes an even more powerful driver.

As large FPGAs become cheaper, both Hybrids and soft cores move into the same general cost area as dedicated processors. At the heart of this argument is also the idea that once you have paid for the FPGA, any extra IP that you place in the device is free functionality.

Avoiding Processor Obsolescence

As products mature, processor supply may become an increasing problem, particularly where the processor is one of many variants supplied by the semiconductor vendor. Switching to a new processor usually requires design software changes or logical hardware changes.

With FPGA implementations, the design can be easily moved to a different device with little or no change to the hardware logic and probably no change to the application software. Peripherals are created dynamically in the hardware, so lack of availability of specific processor variants is never a problem.

The ARM720T_LH79520

Altium Designer's support for the Sharp Bluestreak LH79520 offers you the best of both worlds – allowing you to create designs that themselves reside within an FPGA device, whilst incorporating the processing power of the ARM720T within the physical LH79520 device. Your design may simply provide an extension of the ARM720T to external memory and peripheral devices, the interfacing to which is specified in the design downloaded to the FPGA. Alternatively, you may have a hybrid design, making use not only of a physical processor (and member of the widely regarded ARM7 family), but also one or more 'soft' processors defined within your FPGA design and resident on the target FPGA device. Performance critical code might typically be handled by the physical processor.

The ARM720T is a 32-bit RISC machine that follows the classic RISC architecture previously described. It is a load/store machine with 31 general purpose registers and 6 status registers.

All instructions are 32-bits wide and most execute in a single clock cycle.

The ARM720T_LH79520 also features a user-definable amount of zero-wait state block RAM, with true dual-port access.

Wishbone Bus Interfaces

The ARM720T_LH79520 uses the Wishbone bus standard. This standard is formally described as a “System-on-Chip Interconnection Architecture for Portable IP Cores”. The current standard is the Revision B.3 Specification, a copy of which is included as part of the software installation and can be found by navigating to the Documentation Library » Designing with FPGAs section of the Knowledge Center panel.

The Wishbone standard is not copyrighted and resides in the public domain. It may be freely copied and distributed by any means. Furthermore, it may be used for the design and production of integrated circuit components without royalties or other financial obligations.

Remember that the ARM720T_LH79520 is the 'Wishbone wrapper' placed in your FPGA design. The actual ARM720T resides in the physical LH79520 device – external to the FPGA device to which that design is targeted.

CR0162 (v2.0) March 10, 2008

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Contents Features SummaryAvailable Devices Soft Fpga Processors Why use Soft Processors?Risc Processor Background HistoryWishbone Bus Interfaces ARM720TLH79520Wishbone OpenBUS Processor Wrappers Processor Abstraction SystemDesign Migration Architectural Overview SymbolPin Description Name Type Polarity/Bus size Description Control SignalsPhysical LH79520 Interface Signals Name Type Polarity/Bus size Description Configuring the ProcessorCurrent configuration settings for the processor Memory & I/O Management Defining the Memory MapBuilding the Bridge between the Hardware and Software CR0162 v2.0 March 10 Configuring the Processor Division of Memory SpaceDedicated System Interconnect Components Internal Memory Peripheral I/O External MemoryData Organization Words, Half-Words and BytesPhysical Interface to Memory and Peripherals #define Port32 *volatile unsigned int* Port32Address Interrupts ResetHardware Description ClockingWriting to a Slave Wishbone Memory Device Wishbone CommunicationsWriting to a Slave Wishbone Peripheral Device Reading from a Slave Wishbone Peripheral DeviceWishbone Timing Reading from a Slave Wishbone Memory DevicePlacing an ARM720TLH79520 in an Fpga design Design using a Schematic onlyDesign Featuring an OpenBus System Facilitating Communications Additional Soft Devices in Your Design Downloading Your DesignEnabling the Soft Devices Jtag Chain On-Chip Debugging Accessing the Debug EnvironmentStarting an embedded code debug session CR0162 v2.0 March 10 CR0162 v2.0 March 10 Revision History Instruction Set