SMC Networks ARM720T_LH79520 manual Current configuration settings for the processor

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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor

Speed-critical (or latency-sensitive) parts of an application should also be placed in this memory space.

The following memory sizes are available to choose from:

•1KB (256 x 32-bit Words)

•2KB (512 x 32-bit Words)

•4KB (1K x 32-bit Words)

•8KB (2K x 32-bit Words)

•16KB (4K x 32-bit Words)

•32KB (8K x 32-bit Words)

•64KB (16K x 32-bit Words)

•128KB (32K x 32-bit Words)

•256KB (64K x 32-bit Words)

•512KB (128K x 32-bit Words)

•1MB (256K x 32-bit Words)

When the component is placed on a schematic sheet, your configuration choice will be reflected in the Current Configuration region of the processor’s schematic symbol (Figure 3).

Note: There are no options to remove MDU or Debug Hardware for the ARM720T_LH79520. These architectural features are permanently installed in the actual ARM720T within the physical LH79520 device.

For further information with respect to real-time debugging of the processor, refer to the On-Chip Debugging section of this reference.

Figure 3. Current configuration settings for the processor.

CR0162 (v2.0) March 10, 2008

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Contents
Features SummaryAvailable Devices Risc Processor Background Why use Soft Processors?History Soft Fpga ProcessorsWishbone Bus Interfaces ARM720TLH79520Wishbone OpenBUS Processor Wrappers Processor Abstraction SystemDesign Migration Architectural Overview SymbolPin Description Name Type Polarity/Bus size Description Control SignalsPhysical LH79520 Interface Signals Name Type Polarity/Bus size Description Configuring the ProcessorCurrent configuration settings for the processor Memory & I/O Management Defining the Memory MapBuilding the Bridge between the Hardware and Software CR0162 v2.0 March 10 Configuring the Processor Division of Memory SpaceDedicated System Interconnect Components Internal Memory Peripheral I/O External MemoryData Organization Words, Half-Words and BytesPhysical Interface to Memory and Peripherals #define Port32 *volatile unsigned int* Port32Address Hardware Description ResetClocking InterruptsWriting to a Slave Wishbone Peripheral Device Wishbone CommunicationsReading from a Slave Wishbone Peripheral Device Writing to a Slave Wishbone Memory DeviceWishbone Timing Reading from a Slave Wishbone Memory DevicePlacing an ARM720TLH79520 in an Fpga design Design using a Schematic onlyDesign Featuring an OpenBus System Facilitating Communications Additional Soft Devices in Your Design Downloading Your DesignEnabling the Soft Devices Jtag Chain On-Chip Debugging Accessing the Debug EnvironmentStarting an embedded code debug session CR0162 v2.0 March 10 CR0162 v2.0 March 10 Revision History Instruction Set