SMC Networks LH79520 SoC ARM720T manual Division of Memory Space, Configuring the Processor

ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor

The adjacent flow chart shows the process that was followed to build this memory map in a schematic-based FPGA design. This flow chart is only a guide, during the course of development it is likely that you will jump back and forth through this process as you build up the design.

Place Processor

Dedicated System Interconnect Components

This process of being able to quickly build up the design and resolve the processor to memory & peripheral interface is possible because of specialized interconnection components. On the schematic, these are the Wishbone Interconnect and the Wishbone Multi-Master. In an OpenBus System, these are the Interconnect and Arbiter components.

These components solve the common system interconnect issues that face the designer, these being:

•Interfacing multiple peripheral and memory blocks to a processor (handled by the Interconnect component)

•Allowing two or more system components, that must each be able to control the bus, to share access to a common resource (provided by the Wishbone Multi-Master/Arbiter components)

Use of the Wishbone Interconnection Architecture for all parts of the system connecting to the processor, contributes to the system’s ‘building block’ behavior. The Wishbone standard resolves data exchange between system components – supporting popular data transfer bus protocols, while defining clocking, handshaking and decoding requirements (amongst others).

With the lower-level physical interface requirements being resolved by the Wishbone interface, the other challenge is the structural aspects of the system – defining where components sit address space, providing address decoding, and allocating and interfacing interrupts to the processor.

For more information on the schematic-based Wishbone Interconnect and Wishbone Multi- Master components, refer to the CR0150 WB_INTERCON Configurable Wishbone Interconnect and CR0168 WB_MULTIMASTER Configurable Wishbone Multi-Mastercore references, respectively.

For more information on the OpenBus System-based Interconnect and Arbiter components, refer to the documents TR0170 OpenBus Interconnect Component Reference and TR0171 OpenBus Arbiter Component Reference, respectively.

Place Interconnect

Place peripheral component on document

(peripheral 1)

(peripheral 2)

(peripheral n)

Configure

Interconnect

(Setup P1)

(Setup P2)

(Setup Pn)

Configure Processor

to see Peripherals

(import settings from

Interconnect)

Configuring the Processor

Each configurable component has its own configuration dialog, including the different processors. The processor has separate commands and dialogs to configure memory and peripherals, but it does support mapping peripherals into memory space (and the memory into peripheral space), if required.

An important feature to point out is the Import from Schematic (or Import from OpenBus) button in the processor’s Configure dialogs, clicking this will read in the settings from the Interconnects attached to the processor. This lets you quickly build the memory map, as shown in the figure earlier. You now have the memory map defined in the hardware, this data is stored with the processor component.

Peripheral memory

map ready for

embedded project

(repeat process for

memory)

The flow of connecting and mapping the peripherals (or memory) to the processor in

aschematic-based or OpenBus System-based FPGA design.