SMC Networks LH79520 SoC ARM720T, ARM720T_LH79520 manual Instruction Set, Revision History

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ARM720T_LH79520 – Sharp LH79520 SoC with ARM720T 32-bit RISC Processor

Instruction Set

The ARM7TDMI-S core processor – on which the ARM720T is based – is an implementation of the ARM architecture v4T. For an overview of the ARM instructions available for this processor, refer to the following documents, available from the ARM website:

ARM720T Technical Reference Manual

ARM Instruction Set Quick Reference Card

For detailed information with respect to the ARM instruction set, including instruction encoding and an alphabetical listing of all instructions by mnemonic, refer to a printed publication such as the ARM Architecture Reference Manual.

Revision History

Date

Version No.

 

 

19-Oct-2007

1.0

 

 

10-Mar-2008

2.0

 

 

Revision

Initial release

Updated for Altium Designer Summer 08

Software, hardware, documentation and related materials:

Copyright © 2008 Altium Limited.

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CR0162 (v2.0) March 10, 2008

Image 28 Contents
Summary FeaturesAvailable Devices Why use Soft Processors? Risc Processor BackgroundHistory Soft Fpga ProcessorsARM720TLH79520 Wishbone Bus InterfacesProcessor Abstraction System Wishbone OpenBUS Processor WrappersDesign Migration Symbol Architectural OverviewName Type Polarity/Bus size Description Control Signals Pin DescriptionPhysical LH79520 Interface Signals Configuring the Processor Name Type Polarity/Bus size DescriptionCurrent configuration settings for the processor Defining the Memory Map Memory & I/O ManagementBuilding the Bridge between the Hardware and Software CR0162 v2.0 March 10 Division of Memory Space Configuring the ProcessorDedicated System Interconnect Components Internal Memory External Memory Peripheral I/OWords, Half-Words and Bytes Data OrganizationPhysical Interface to Memory and Peripherals #define Port32 *volatile unsigned int* Port32Address Reset Hardware DescriptionClocking InterruptsWishbone Communications Writing to a Slave Wishbone Peripheral DeviceReading from a Slave Wishbone Peripheral Device Writing to a Slave Wishbone Memory DeviceReading from a Slave Wishbone Memory Device Wishbone TimingDesign using a Schematic only Placing an ARM720TLH79520 in an Fpga designDesign Featuring an OpenBus System Facilitating Communications Downloading Your Design Additional Soft Devices in Your DesignEnabling the Soft Devices Jtag Chain Accessing the Debug Environment On-Chip DebuggingStarting an embedded code debug session CR0162 v2.0 March 10 CR0162 v2.0 March 10 Instruction Set Revision History