Omega OME-A822PG manual 1 8254 Counter, 2 A/D Input Buffer Register

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2.4.18254 Counter

The 8254 Programmable timer/counter has 4 registers from Base+0 through Base+3. For detailed programming information on the 8254 , please refer to Intel‘s “Microsystem Components Handbook”.

Address	Read	Write
Base+0	8254 Counter 0	8254	Counter 0
Base+1	8254 Counter 1	8254	Counter 1
Base+2	8254 Counter 2	8254	Counter 2
Base+3	Reserved	8254	Counter Control

2.4.2A/D Input Buffer Register

(READ)	Base+4 : A/D Low Byte Data Format
Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
D7	D6	D5	D4	D3	D2	D1	D0
(READ)	Base+5 : A/D High Byte Data Format
Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
0	0	0	READY	D11	D10	D9	D8

A/D 12 bit data : D11…..D0, D11=MSB, D0=LSB

READY =1 : A/D 12 bit data not ready =0 : A/D 12 bit data is ready

The low 8 bit A/D data is stored in address BASE+4 and the high 4 bit data is stored in address BASE+5. The READY bit is used as an indicator for the A/D conversion. When an

A/D conversion is completed, the READY bit will clear to zero.

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Contents User’sGuide Czech Republic CanadaMexico BeneluxOME-A-822PGH/PGL Introduction Tables of ContentsConnector General Description Features3 A/D Converter SpecificationsPower Consumption Analog InputsDigital I/O DA ConverterInterrupt Channel Direct Memory Access Channel DMA Programmable Timer/CounterProduct Check List ApplicationsBoard Layout Hardware ConfigurationDefault base address is I/O Base Address Setting1 JP1 D/A Internal Reference Voltage Selection Jumper Settings3 JP3 Single-ended/Differential Selection 2 JP2 D/A Int/Ext Ref Voltage Selection5 JP5 Interrupt Level Selection 4 JP4 A/D Trigger Source Selection6 JP6 User Timer/Counter Clock Input Selection DRQ JP7 Dack JP8 DMA 7 JP7 DMA Dack Selection JP8 DMA DRQ SelectionAddress Read Write I/O Register Address2 A/D Input Buffer Register 1 8254 CounterConversion is completed, the Ready bit will clear to zero 3 D/A Output Latch Register Clear Interrupt Request 4 D/I Input Buffer RegisterGAIN3 GAIN2 GAIN1 GAIN0 6 A/D Gain Control Register7 A/D Multiplex Control Register OME-A-822PGH Gain Control Code Table8 A/D Mode Control Register 9 A/D Software Trigger Control Register 10 D/O Output Latch Register CN2 Digital I/OCounter 8254 Timer/CounterA/D Conversion Polling, interrupt and DMA 1 A/D conversion flow3 A/D Transfer Modes 2 A/D Conversion Trigger ModesDelay the settling time refer to Sec .4.6 and Sec Using software trigger and polling transferRefer to Sec D/A Conversion Analog Input Signal Connection OME-A-822PGL/PGH Hardware Manual OME-A-822PGL/PGH Hardware Manual Use a single connection to frame ground not A.GND or D.GND Signal ShieldingUsing OME-DB-8225 CJC Output CN1 Digital Input Pin Assignment CN1/CN2/CN3 Pin AssignmentCN2 Digital Output Pin Assignment SINGLE-ENDED Signal Mode Differential Signals OME-DB-16P Daughter BoardOME-DB-8225 OME-DB-37Description of Variable Resistors CalibrationD/A Calibration A/D Calibration Introduction Diagnostic UtilityOME-A-822PGL/PGH Hardware Manual Running The Diagnostic Utility Base address selection screen SetupDMA no and IRQ no selection screen Calibration Function Test Test Test Screen Digital I/O Test Screen Multiplexer Test Screen Use IRQ Test Screen Use DMA Test Screen DA Gain Test Screen Timer 0 Test Screen Special Test Help WARRANTY/DISCLAIMER Temperature