Omega OME-A822PG manual A/D Calibration

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4.3 A/D Calibration

1.Run the A82XDIAG.EXE

2.Press “Right Arrow Key” to select “CALIBRATION”

3.Press the “Down Arrow Key” to select “C. A/D REFERENCE” item.

4.Press the “Enter Key”

5.Input a stable 4.9988V to A/D channel 0, pin 1 of CN3

6.Adjust VR2 until the A/D data shown on the screen is between 4094 to 4095

7.Press the “ESC Key”

8.Select and Execute the “D. A/D OFFSET” item

9.Input a stable 0V to A/D channel 0, pin1 of CN3

10.Adjust VR1 until the A/D data shown on the screen is between 2048 to 2049

11.Press the “ESC Key”

12.Repeat step_3 to step_11 until there is no need to adjust VR2,VR1

13.Select and Execute “E. PGA OFFSET” item

14.Input a stable 0V to A/D channel 0, pin 1 of CN3

15.Adjust VR7 until the A/D data shown in screen between 2048 to 2049

16.Press “ESC Key”

17. Select and Execute “F. PGA REFERENCE” item

18.Input a stable 0V to A/D channel 0 , pin1 of CN3

19.Adjust VR6 until the A/D data shown on screen is between 0 and 1

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Contents User’sGuide Mexico CanadaBenelux Czech RepublicOME-A-822PGH/PGL Introduction Tables of ContentsConnector General Description FeaturesPower Consumption SpecificationsAnalog Inputs 3 A/D ConverterDA Converter Digital I/OInterrupt Channel Direct Memory Access Channel DMA Programmable Timer/CounterProduct Check List ApplicationsBoard Layout Hardware ConfigurationDefault base address is I/O Base Address Setting1 JP1 D/A Internal Reference Voltage Selection Jumper Settings3 JP3 Single-ended/Differential Selection 2 JP2 D/A Int/Ext Ref Voltage Selection5 JP5 Interrupt Level Selection 4 JP4 A/D Trigger Source Selection6 JP6 User Timer/Counter Clock Input Selection DRQ JP7 Dack JP8 DMA 7 JP7 DMA Dack Selection JP8 DMA DRQ SelectionAddress Read Write I/O Register Address1 8254 Counter 2 A/D Input Buffer RegisterConversion is completed, the Ready bit will clear to zero 3 D/A Output Latch Register Clear Interrupt Request 4 D/I Input Buffer RegisterGAIN3 GAIN2 GAIN1 GAIN0 6 A/D Gain Control Register7 A/D Multiplex Control Register OME-A-822PGH Gain Control Code Table8 A/D Mode Control Register 9 A/D Software Trigger Control Register 10 D/O Output Latch Register CN2 Digital I/OCounter 8254 Timer/CounterA/D Conversion Polling, interrupt and DMA 1 A/D conversion flow3 A/D Transfer Modes 2 A/D Conversion Trigger ModesUsing software trigger and polling transfer Delay the settling time refer to Sec .4.6 and SecRefer to Sec D/A Conversion Analog Input Signal Connection OME-A-822PGL/PGH Hardware Manual OME-A-822PGL/PGH Hardware Manual Use a single connection to frame ground not A.GND or D.GND Signal ShieldingUsing OME-DB-8225 CJC Output CN1/CN2/CN3 Pin Assignment CN1 Digital Input Pin AssignmentCN2 Digital Output Pin Assignment SINGLE-ENDED Signal Mode Differential Signals OME-DB-8225 Daughter BoardOME-DB-37 OME-DB-16PDescription of Variable Resistors CalibrationD/A Calibration A/D Calibration Introduction Diagnostic UtilityOME-A-822PGL/PGH Hardware Manual Running The Diagnostic Utility Base address selection screen SetupDMA no and IRQ no selection screen Calibration Function Test Test Test Screen Digital I/O Test Screen Multiplexer Test Screen Use IRQ Test Screen Use DMA Test Screen DA Gain Test Screen Timer 0 Test Screen Special Test Help WARRANTY/DISCLAIMER Temperature