Omega OME-A822PG manual 3 D/A Output Latch Register

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2.4.3D/A Output Latch Register

(WRITE)	Base+4 : Channel 1 D/A Low Byte Data Format
Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
D7	D6	D5	D4	D3	D2	D1	D0
(WRITE)	Base+5 :Channel 1 D/A High Byte Data Format
Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
X	X	X	X	D11	D10	D9	D8
(WRITE)	Base+6 : Channel 2 D/A Low Byte Data Format
Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
D7	D6	D5	D4	D3	D2	D1	D0
(WRITE)	Base+7 :Channel 2 D/A High Byte Data Format
Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
X	X	X	X	D11	D10	D9	D8

D/A 12 bit output data: D11..D0, D11=MSB, D0=LSB, X=don‘t care

The D/A converter will convert the 12 bit digital data to an analog output. The lower 8 bits of D/A channel 1 are stored in the address BASE+4 and the high 4 bits are stored in the address BASE+5. The address BASE+6 and BASE+7 store the 12 bit data for D/A channel 2. The D/A output latch registers are designed with a “double buffered” structure, so the analog output latch registers will not update until the high 4 bit digital data are written. If the user sends the high 4 bit data first, the D/A 12 bit output latch registers will update at once. So the lower 8 bits will be the previous data latched in the register. This action will cause an error on the D/A output voltage. The user must send the low 8 bits first and then send the high 4 bits to update the 12 bit D/A output latch register.

NOTE : Send the low 8 bits first, then send the high 4 bits.

OME-A-822PGL/PGH Hardware Manual ---- 18

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Contents User’sGuide Canada MexicoBenelux Czech RepublicOME-A-822PGH/PGL Tables of Contents IntroductionConnector Features General DescriptionSpecifications Power ConsumptionAnalog Inputs 3 A/D ConverterInterrupt Channel DA ConverterDigital I/O Programmable Timer/Counter Direct Memory Access Channel DMAApplications Product Check ListHardware Configuration Board LayoutI/O Base Address Setting Default base address isJumper Settings 1 JP1 D/A Internal Reference Voltage Selection2 JP2 D/A Int/Ext Ref Voltage Selection 3 JP3 Single-ended/Differential Selection4 JP4 A/D Trigger Source Selection 5 JP5 Interrupt Level Selection6 JP6 User Timer/Counter Clock Input Selection 7 JP7 DMA Dack Selection JP8 DMA DRQ Selection DRQ JP7 Dack JP8 DMAI/O Register Address Address Read WriteConversion is completed, the Ready bit will clear to zero 1 8254 Counter2 A/D Input Buffer Register 3 D/A Output Latch Register 4 D/I Input Buffer Register Clear Interrupt Request6 A/D Gain Control Register GAIN3 GAIN2 GAIN1 GAIN0OME-A-822PGH Gain Control Code Table 7 A/D Multiplex Control Register8 A/D Mode Control Register 9 A/D Software Trigger Control Register 10 D/O Output Latch Register Digital I/O CN28254 Timer/Counter CounterA/D Conversion 1 A/D conversion flow Polling, interrupt and DMA2 A/D Conversion Trigger Modes 3 A/D Transfer ModesRefer to Sec Using software trigger and polling transferDelay the settling time refer to Sec .4.6 and Sec D/A Conversion Analog Input Signal Connection OME-A-822PGL/PGH Hardware Manual OME-A-822PGL/PGH Hardware Manual Signal Shielding Use a single connection to frame ground not A.GND or D.GNDUsing OME-DB-8225 CJC Output CN2 Digital Output Pin Assignment CN1/CN2/CN3 Pin AssignmentCN1 Digital Input Pin Assignment SINGLE-ENDED Signal Mode Differential Signals Daughter Board OME-DB-8225OME-DB-37 OME-DB-16PCalibration Description of Variable ResistorsD/A Calibration A/D Calibration Diagnostic Utility IntroductionOME-A-822PGL/PGH Hardware Manual Running The Diagnostic Utility Setup Base address selection screenDMA no and IRQ no selection screen Calibration Function Test Test Test Screen Digital I/O Test Screen Multiplexer Test Screen Use IRQ Test Screen Use DMA Test Screen DA Gain Test Screen Timer 0 Test Screen Special Test Help WARRANTY/DISCLAIMER Temperature