Omega OME-A822PG manual 2 A/D Conversion Trigger Modes, 3 A/D Transfer Modes

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2.7.2A/D Conversion Trigger Modes

OME-A-822PGL/PGH supports three trigger modes.

1 : Software Trigger :

Write any value to the A/D software trigger control register, BASE+A, to initiate an A/D conversion cycle. This mode is very simple but it is very difficult to achieve a precise sample rate.

2 : Pacer Trigger Mode :

The block diagram of the pacer timer is shown in section 2.6. The pacer timer can provide a very precise sample rate.

3 : External Trigger Mode :

When a rising edge of an external trigger signal is applied, an A/D conversion will be performed. The external trigger source comes from pin 17 of CN3.

2.7.3A/D Transfer Modes

OME-A-822PGL/PGH supports three transfer modes.

1 : polling transfer :

This mode can be used with all trigger modes. More detailed information is given in section 2.4.8. The software scans the A/D high byte data register, BASE+5, until READY_BIT=0.The low byte data is available in BASE+4.

2 : interrupt transfer :

This mode can be used with the pacer trigger or external trigger. More detailed information is given in section 2.4.8.The user can set the IRQ level by adjusting jumper JP5. A hardware interrupt signal is sent to the PC when an A/D conversion is

3 : compDMAletedrans. fer :

This mode can be used with the pacer trigger or external trigger. More detailed information is given in section 2.4.8. The user can set the DMA channel by adjusting jumpers JP7 and JP8. Two hardware DMA requests signals are sent sequentially to the PC when an A/D conversion is completed. The single mode transfer of the 8237 is suggested.

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Contents User’sGuide Czech Republic CanadaMexico BeneluxOME-A-822PGH/PGL Introduction Tables of ContentsConnector General Description Features3 A/D Converter SpecificationsPower Consumption Analog InputsDigital I/O DA ConverterInterrupt Channel Direct Memory Access Channel DMA Programmable Timer/CounterProduct Check List ApplicationsBoard Layout Hardware ConfigurationDefault base address is I/O Base Address Setting1 JP1 D/A Internal Reference Voltage Selection Jumper Settings3 JP3 Single-ended/Differential Selection 2 JP2 D/A Int/Ext Ref Voltage Selection5 JP5 Interrupt Level Selection 4 JP4 A/D Trigger Source Selection6 JP6 User Timer/Counter Clock Input Selection DRQ JP7 Dack JP8 DMA 7 JP7 DMA Dack Selection JP8 DMA DRQ SelectionAddress Read Write I/O Register Address2 A/D Input Buffer Register 1 8254 CounterConversion is completed, the Ready bit will clear to zero 3 D/A Output Latch Register Clear Interrupt Request 4 D/I Input Buffer RegisterGAIN3 GAIN2 GAIN1 GAIN0 6 A/D Gain Control Register7 A/D Multiplex Control Register OME-A-822PGH Gain Control Code Table8 A/D Mode Control Register 9 A/D Software Trigger Control Register 10 D/O Output Latch Register CN2 Digital I/OCounter 8254 Timer/CounterA/D Conversion Polling, interrupt and DMA 1 A/D conversion flow3 A/D Transfer Modes 2 A/D Conversion Trigger ModesDelay the settling time refer to Sec .4.6 and Sec Using software trigger and polling transferRefer to Sec D/A Conversion Analog Input Signal Connection OME-A-822PGL/PGH Hardware Manual OME-A-822PGL/PGH Hardware Manual Use a single connection to frame ground not A.GND or D.GND Signal ShieldingUsing OME-DB-8225 CJC Output CN1 Digital Input Pin Assignment CN1/CN2/CN3 Pin AssignmentCN2 Digital Output Pin Assignment SINGLE-ENDED Signal Mode Differential Signals OME-DB-16P Daughter BoardOME-DB-8225 OME-DB-37Description of Variable Resistors CalibrationD/A Calibration A/D Calibration Introduction Diagnostic UtilityOME-A-822PGL/PGH Hardware Manual Running The Diagnostic Utility Base address selection screen SetupDMA no and IRQ no selection screen Calibration Function Test Test Test Screen Digital I/O Test Screen Multiplexer Test Screen Use IRQ Test Screen Use DMA Test Screen DA Gain Test Screen Timer 0 Test Screen Special Test Help WARRANTY/DISCLAIMER Temperature