Omega OME-A822PG manual A/D Conversion

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2.7 A/D Conversion

This section explains how to perform A/D conversions. The A/D conversion can be triggered 3 ways, by software trigger, by pacer trigger or by external trigger to the A/D converter. At the end of A/D conversion, it is possible to transfer data by 3 ways, those are polling , interrupt and DMA. Before using the A/D conversion functions, the user should be aware of the following issues:

zA/D data register BASE+4/BASE+5 stores the A/D conversion data (sec. 2.4.2)

zA/D gain control register BASE+9 selects the gain (sec. 2.4.6)

zA/D multiplexer control register BASE+A selects the analog input channel (sec. 2.4.7)

zA/D mode control register BASE+B selects the trigger type and transfer type (sec. 2.4.8)

zA/D software trigger control register is BASE+C (sec. 2.4.9)

zJP3 selects single-ended or differential input (sec. 2.3.3)

zJP4 selects internal/external trigger (sec. 2.3.4)

zJP5 selects the IRQ level (sec. 2.3.5)

zJP6 selects the internal/external clock for counter0 (sec. 2.3.6)

zJP7 and JP8 selects the DMA channel (sec. 2.3.7)

zThere are 3 trigger types : software, pacer, external trigger (sec. 2.4.8)

zThere are 3 transfer types : polling, interrupt, DMA (sec. 2.4.8)

The block diagram is given below:

CN3	16/8 to 1	Gain	12 bits
	Multi-	control	A/D		Buffer		Memory
	plexer
	Base+A	Base+9	Trigger		Transfer		CPU
			Logic		Logic
	JP3	Base+C	JP4	Base+B		JP5
OME-A-822PGL/PGH						JP7
OME-A-822PGL/PGH						JP8
						JP8
	OME-A-822PGL/PGH Hardware Manual					---- 27

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Contents User’sGuide Mexico CanadaBenelux Czech RepublicOME-A-822PGH/PGL Introduction Tables of ContentsConnector General Description FeaturesPower Consumption SpecificationsAnalog Inputs 3 A/D ConverterInterrupt Channel DA ConverterDigital I/O Direct Memory Access Channel DMA Programmable Timer/CounterProduct Check List ApplicationsBoard Layout Hardware ConfigurationDefault base address is I/O Base Address Setting1 JP1 D/A Internal Reference Voltage Selection Jumper Settings3 JP3 Single-ended/Differential Selection 2 JP2 D/A Int/Ext Ref Voltage Selection5 JP5 Interrupt Level Selection 4 JP4 A/D Trigger Source Selection6 JP6 User Timer/Counter Clock Input Selection DRQ JP7 Dack JP8 DMA 7 JP7 DMA Dack Selection JP8 DMA DRQ SelectionAddress Read Write I/O Register AddressConversion is completed, the Ready bit will clear to zero 1 8254 Counter2 A/D Input Buffer Register 3 D/A Output Latch Register Clear Interrupt Request 4 D/I Input Buffer RegisterGAIN3 GAIN2 GAIN1 GAIN0 6 A/D Gain Control Register7 A/D Multiplex Control Register OME-A-822PGH Gain Control Code Table8 A/D Mode Control Register 9 A/D Software Trigger Control Register 10 D/O Output Latch Register CN2 Digital I/OCounter 8254 Timer/CounterA/D Conversion Polling, interrupt and DMA 1 A/D conversion flow3 A/D Transfer Modes 2 A/D Conversion Trigger ModesRefer to Sec Using software trigger and polling transferDelay the settling time refer to Sec .4.6 and Sec D/A Conversion Analog Input Signal Connection OME-A-822PGL/PGH Hardware Manual OME-A-822PGL/PGH Hardware Manual Use a single connection to frame ground not A.GND or D.GND Signal ShieldingUsing OME-DB-8225 CJC Output CN2 Digital Output Pin Assignment CN1/CN2/CN3 Pin AssignmentCN1 Digital Input Pin Assignment SINGLE-ENDED Signal Mode Differential Signals OME-DB-8225 Daughter BoardOME-DB-37 OME-DB-16PDescription of Variable Resistors CalibrationD/A Calibration A/D Calibration Introduction Diagnostic UtilityOME-A-822PGL/PGH Hardware Manual Running The Diagnostic Utility Base address selection screen SetupDMA no and IRQ no selection screen Calibration Function Test Test Test Screen Digital I/O Test Screen Multiplexer Test Screen Use IRQ Test Screen Use DMA Test Screen DA Gain Test Screen Timer 0 Test Screen Special Test Help WARRANTY/DISCLAIMER Temperature