Omega OME-A822PG manual Digital I/O, CN2

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2.5 Digital I/O

The OME-A-822PGL/PGH provides 16 digital input channels and 16 digital output channels. All levels are TTL compatible. The connection diagram and block diagram are given below:

	Output Latch Register
Base+D	Latch	CN2
		CN2
D0..D7	D0..D7	1..8	TTL	DI
		1..8	TTL	DI
Power on	Reset	17..18		DGND
reset	Reset	DGND
	Reset
	D8..D15	9..16
	D8..D15
Base+E	Latch			External
				External
	Output Latch Register			Device
	OME-A-822PGL/PGH

	Input Buffer Register	OME-A-822PGL/PGH
Base+6	Read	CN1
		CN1
D0..D7	D0..D7	1..8	TTL
		1..8	TTL
	D8..D15	17..18
	D8..D15	DGND
		DGND
Base+7	Read	9..16
		9..16
	Input Buffer Register

DO

DGND

External

Device

OME-A-822PGL/PGH Hardware Manual ---- 25

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Contents User’sGuide Czech Republic CanadaMexico BeneluxOME-A-822PGH/PGL Introduction Tables of ContentsConnector General Description Features3 A/D Converter SpecificationsPower Consumption Analog InputsDA Converter Digital I/OInterrupt Channel Direct Memory Access Channel DMA Programmable Timer/CounterProduct Check List ApplicationsBoard Layout Hardware ConfigurationDefault base address is I/O Base Address Setting1 JP1 D/A Internal Reference Voltage Selection Jumper Settings3 JP3 Single-ended/Differential Selection 2 JP2 D/A Int/Ext Ref Voltage Selection5 JP5 Interrupt Level Selection 4 JP4 A/D Trigger Source Selection6 JP6 User Timer/Counter Clock Input Selection DRQ JP7 Dack JP8 DMA 7 JP7 DMA Dack Selection JP8 DMA DRQ SelectionAddress Read Write I/O Register Address1 8254 Counter 2 A/D Input Buffer RegisterConversion is completed, the Ready bit will clear to zero 3 D/A Output Latch Register Clear Interrupt Request 4 D/I Input Buffer RegisterGAIN3 GAIN2 GAIN1 GAIN0 6 A/D Gain Control Register7 A/D Multiplex Control Register OME-A-822PGH Gain Control Code Table8 A/D Mode Control Register 9 A/D Software Trigger Control Register 10 D/O Output Latch Register CN2 Digital I/OCounter 8254 Timer/CounterA/D Conversion Polling, interrupt and DMA 1 A/D conversion flow3 A/D Transfer Modes 2 A/D Conversion Trigger ModesUsing software trigger and polling transfer Delay the settling time refer to Sec .4.6 and SecRefer to Sec D/A Conversion Analog Input Signal Connection OME-A-822PGL/PGH Hardware Manual OME-A-822PGL/PGH Hardware Manual Use a single connection to frame ground not A.GND or D.GND Signal ShieldingUsing OME-DB-8225 CJC Output CN1/CN2/CN3 Pin Assignment CN1 Digital Input Pin AssignmentCN2 Digital Output Pin Assignment SINGLE-ENDED Signal Mode Differential Signals OME-DB-16P Daughter BoardOME-DB-8225 OME-DB-37Description of Variable Resistors CalibrationD/A Calibration A/D Calibration Introduction Diagnostic UtilityOME-A-822PGL/PGH Hardware Manual Running The Diagnostic Utility Base address selection screen SetupDMA no and IRQ no selection screen Calibration Function Test Test Test Screen Digital I/O Test Screen Multiplexer Test Screen Use IRQ Test Screen Use DMA Test Screen DA Gain Test Screen Timer 0 Test Screen Special Test Help WARRANTY/DISCLAIMER Temperature