Omega OME-A822PG manual SINGLE-ENDED Signal Mode

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SINGLE-ENDED SIGNAL MODE

CN3 : Analog input, Analog output and Timer/Counter Pin Assignment.

Pin Number

Description

Pin Number

Description

1

Analog Input 0/+

20

Analog Input 8/+

2

Analog Input 1/+

21

Analog Input 9/+

3

Analog Input 2/+

22

Analog Input 10/+

4

Analog Input 3/+

23

Analog Input 11/+

5

Analog Input 4/+

24

Analog Input 12/+

6

Analog Input 5/+

25

Analog Input 13/+

7

Analog Input 6/+

26

Analog Input 14/+

8

Analog Input 7/+

27

Analog Input 15/+

9

Analog GND

28

Analog GND

10

Analog GND

29

Analog GND

11

D/A internal -5V/-10V

30

D/A channel 0 analog

 

voltage reference

 

voltage output

12

D/A channel 1 external

31

D/A channel 0 external

 

voltage reference input

 

voltage reference input

13

+12V Output

32

D/A channel 1 analog

 

 

 

voltage output

14

PCB analog GND

33

User timer/counter‘s

 

 

 

GATE control input

15

PCB digital GND

34

Timer/counter 1&2 GATE

 

 

 

control input

16

User timer/counter output

35

Timer/counter 1 output

17

External trigger source

36

Reserved

 

input/TTL

 

 

18

Reserved

37

User timer/counter external

 

 

 

clock input (internal=2M)

19

+5V Output

XXXXXXX

This pin not available

OME-A-822PGL/PGH Hardware Manual ---- 38

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Contents User’sGuide Canada MexicoBenelux Czech RepublicOME-A-822PGH/PGL Tables of Contents IntroductionConnector Features General DescriptionSpecifications Power ConsumptionAnalog Inputs 3 A/D ConverterDigital I/O DA ConverterInterrupt Channel Programmable Timer/Counter Direct Memory Access Channel DMAApplications Product Check ListHardware Configuration Board LayoutI/O Base Address Setting Default base address isJumper Settings 1 JP1 D/A Internal Reference Voltage Selection2 JP2 D/A Int/Ext Ref Voltage Selection 3 JP3 Single-ended/Differential Selection4 JP4 A/D Trigger Source Selection 5 JP5 Interrupt Level Selection6 JP6 User Timer/Counter Clock Input Selection 7 JP7 DMA Dack Selection JP8 DMA DRQ Selection DRQ JP7 Dack JP8 DMAI/O Register Address Address Read Write2 A/D Input Buffer Register 1 8254 CounterConversion is completed, the Ready bit will clear to zero 3 D/A Output Latch Register 4 D/I Input Buffer Register Clear Interrupt Request6 A/D Gain Control Register GAIN3 GAIN2 GAIN1 GAIN0OME-A-822PGH Gain Control Code Table 7 A/D Multiplex Control Register8 A/D Mode Control Register 9 A/D Software Trigger Control Register 10 D/O Output Latch Register Digital I/O CN28254 Timer/Counter CounterA/D Conversion 1 A/D conversion flow Polling, interrupt and DMA2 A/D Conversion Trigger Modes 3 A/D Transfer ModesDelay the settling time refer to Sec .4.6 and Sec Using software trigger and polling transferRefer to Sec D/A Conversion Analog Input Signal Connection OME-A-822PGL/PGH Hardware Manual OME-A-822PGL/PGH Hardware Manual Signal Shielding Use a single connection to frame ground not A.GND or D.GNDUsing OME-DB-8225 CJC Output CN1 Digital Input Pin Assignment CN1/CN2/CN3 Pin AssignmentCN2 Digital Output Pin Assignment SINGLE-ENDED Signal Mode Differential Signals Daughter Board OME-DB-8225OME-DB-37 OME-DB-16PCalibration Description of Variable ResistorsD/A Calibration A/D Calibration Diagnostic Utility IntroductionOME-A-822PGL/PGH Hardware Manual Running The Diagnostic Utility Setup Base address selection screenDMA no and IRQ no selection screen Calibration Function Test Test Test Screen Digital I/O Test Screen Multiplexer Test Screen Use IRQ Test Screen Use DMA Test Screen DA Gain Test Screen Timer 0 Test Screen Special Test Help WARRANTY/DISCLAIMER Temperature