Omega OME-A822PG manual D/A Conversion

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2.8 D/A Conversion

The OME-A-822PGL/PGH provides two 12 bit D/A converters. Before using the D/A converter function, you should address the following items:

zD/A output register, BASE+4/BASE+5/BASE+6/BASE+7, (sec. 2.4.3)

zJP1 jumper set to internal reference voltage -5V or -10V (sec. 2.3.1)

zJP2 jumper set to internal or external reference voltage (sec. 2.3.2)

zIf JP2 is set to internal and JP1 is set to -5V, the D/A output range is 0 to 5V

zIf JP2 is set to internal and JP1 is set to -10V, the D/A output range is 0 to 10V

zIf JP2 is set to external, the external reference voltage can be AC/DC +/- 10V

The block diagram is given below:

 

 

 

CN3

 

 

D/A channel 0

V0+

V0-

 

 

 

D0..D7

Base+4/+5

30

 

 

 

 

 

Ref

9,10,14,28,29

 

 

 

 

 

-5/-10 V

JP1

Analog

31

 

Gnd

 

 

 

 

Internal

JP2

Vref0+

Vref0-

 

Reference

 

Vref1+

Vref1-

 

 

 

 

 

Ref

12

 

 

Base+6/+7

V1+

V1-

 

D/A channel 1

32

 

OME-A-822PGL/PGH

 

 

 

 

 

 

NOTE : The D/A output latch registers use a “double buffer” structure. The user must

send the low byte data first, then send the high byte data. If the user

only sends the high byte, the low byte data will be the previous value.

OME-A-822PGL/PGH Hardware Manual ---- 31

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Contents User’sGuide Mexico CanadaBenelux Czech RepublicOME-A-822PGH/PGL Introduction Tables of ContentsConnector General Description FeaturesPower Consumption SpecificationsAnalog Inputs 3 A/D ConverterDA Converter Digital I/OInterrupt Channel Direct Memory Access Channel DMA Programmable Timer/CounterProduct Check List ApplicationsBoard Layout Hardware ConfigurationDefault base address is I/O Base Address Setting1 JP1 D/A Internal Reference Voltage Selection Jumper Settings3 JP3 Single-ended/Differential Selection 2 JP2 D/A Int/Ext Ref Voltage Selection5 JP5 Interrupt Level Selection 4 JP4 A/D Trigger Source Selection6 JP6 User Timer/Counter Clock Input Selection DRQ JP7 Dack JP8 DMA 7 JP7 DMA Dack Selection JP8 DMA DRQ SelectionAddress Read Write I/O Register Address1 8254 Counter 2 A/D Input Buffer RegisterConversion is completed, the Ready bit will clear to zero 3 D/A Output Latch Register Clear Interrupt Request 4 D/I Input Buffer RegisterGAIN3 GAIN2 GAIN1 GAIN0 6 A/D Gain Control Register7 A/D Multiplex Control Register OME-A-822PGH Gain Control Code Table8 A/D Mode Control Register 9 A/D Software Trigger Control Register 10 D/O Output Latch Register CN2 Digital I/OCounter 8254 Timer/CounterA/D Conversion Polling, interrupt and DMA 1 A/D conversion flow3 A/D Transfer Modes 2 A/D Conversion Trigger ModesUsing software trigger and polling transfer Delay the settling time refer to Sec .4.6 and SecRefer to Sec D/A Conversion Analog Input Signal Connection OME-A-822PGL/PGH Hardware Manual OME-A-822PGL/PGH Hardware Manual Use a single connection to frame ground not A.GND or D.GND Signal ShieldingUsing OME-DB-8225 CJC Output CN1/CN2/CN3 Pin Assignment CN1 Digital Input Pin AssignmentCN2 Digital Output Pin Assignment SINGLE-ENDED Signal Mode Differential Signals OME-DB-8225 Daughter BoardOME-DB-37 OME-DB-16PDescription of Variable Resistors CalibrationD/A Calibration A/D Calibration Introduction Diagnostic UtilityOME-A-822PGL/PGH Hardware Manual Running The Diagnostic Utility Base address selection screen SetupDMA no and IRQ no selection screen Calibration Function Test Test Test Screen Digital I/O Test Screen Multiplexer Test Screen Use IRQ Test Screen Use DMA Test Screen DA Gain Test Screen Timer 0 Test Screen Special Test Help WARRANTY/DISCLAIMER Temperature
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