Omega OME-A822PG manual CN1/CN2/CN3 Pin Assignment, CN1 Digital Input Pin Assignment

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3.Connector

The OME-A-822PGL/PGH provides three connectors. Connector 1, CN1

contains the 16 digital inputs. Connector 2, CN2, contains the 16 digital outputs. Connector 3, CN3, contains the analog inputs, analog outputs and timer/counter I/O.

3.1 CN1/CN2/CN3 Pin Assignment

CN1 : Digital Input Pin Assignment.

Pin Number	Description	Pin Number	Description
1	Digital Input 0/TTL	2	Digital Input 1/TTL
3	Digital Input 2/TTL	4	Digital Input 3/TTL
5	Digital Input 4/TTL	6	Digital Input 5/TTL
7	Digital Input 6/TTL	8	Digital Input 7/TTL
9	Digital Input 8/TTL	10	Digital Input 9/TTL
11	Digital Input 10/TTL	12	Digital Input 11/TTL
13	Digital Input 12/TTL	14	Digital Input 13/TTL
15	Digital Input 14/TTL	16	Digital Input 15/TTL
17	GND	18	GND
19	+5V Output	20	+12V Output
CN2 : Digital Output Pin Assignment.
Pin Number	Description	Pin Number	Description
1	Digital Output 0/TTL	2	Digital Output 1/TTL
3	Digital Output 2/TTL	4	Digital Output 3/TTL
5	Digital Output 4/TTL	6	Digital Output 5/TTL
7	Digital Output 6/TTL	8	Digital Output 7/TTL
9	Digital Output 8/TTL	10	Digital Output 9/TTL
11	Digital Output 10/TTL	12	Digital Output 11/TTL
13	Digital Output 12/TTL	14	Digital Output 13TTL
15	Digital Output 14/TTL	16	Digital Output 15/TTL
17	GND	18	GND
19	+5V Output	20	+12 OutputV

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Contents User’sGuide Czech Republic CanadaMexico BeneluxOME-A-822PGH/PGL Introduction Tables of ContentsConnector General Description Features3 A/D Converter SpecificationsPower Consumption Analog InputsDA Converter Digital I/OInterrupt Channel Direct Memory Access Channel DMA Programmable Timer/CounterProduct Check List ApplicationsBoard Layout Hardware ConfigurationDefault base address is I/O Base Address Setting1 JP1 D/A Internal Reference Voltage Selection Jumper Settings3 JP3 Single-ended/Differential Selection 2 JP2 D/A Int/Ext Ref Voltage Selection5 JP5 Interrupt Level Selection 4 JP4 A/D Trigger Source Selection6 JP6 User Timer/Counter Clock Input Selection DRQ JP7 Dack JP8 DMA 7 JP7 DMA Dack Selection JP8 DMA DRQ SelectionAddress Read Write I/O Register Address1 8254 Counter 2 A/D Input Buffer RegisterConversion is completed, the Ready bit will clear to zero 3 D/A Output Latch Register Clear Interrupt Request 4 D/I Input Buffer RegisterGAIN3 GAIN2 GAIN1 GAIN0 6 A/D Gain Control Register7 A/D Multiplex Control Register OME-A-822PGH Gain Control Code Table8 A/D Mode Control Register 9 A/D Software Trigger Control Register 10 D/O Output Latch Register CN2 Digital I/OCounter 8254 Timer/CounterA/D Conversion Polling, interrupt and DMA 1 A/D conversion flow3 A/D Transfer Modes 2 A/D Conversion Trigger ModesUsing software trigger and polling transfer Delay the settling time refer to Sec .4.6 and SecRefer to Sec D/A Conversion Analog Input Signal Connection OME-A-822PGL/PGH Hardware Manual OME-A-822PGL/PGH Hardware Manual Use a single connection to frame ground not A.GND or D.GND Signal ShieldingUsing OME-DB-8225 CJC Output CN1/CN2/CN3 Pin Assignment CN1 Digital Input Pin AssignmentCN2 Digital Output Pin Assignment SINGLE-ENDED Signal Mode Differential Signals OME-DB-16P Daughter BoardOME-DB-8225 OME-DB-37Description of Variable Resistors CalibrationD/A Calibration A/D Calibration Introduction Diagnostic UtilityOME-A-822PGL/PGH Hardware Manual Running The Diagnostic Utility Base address selection screen SetupDMA no and IRQ no selection screen Calibration Function Test Test Test Screen Digital I/O Test Screen Multiplexer Test Screen Use IRQ Test Screen Use DMA Test Screen DA Gain Test Screen Timer 0 Test Screen Special Test Help WARRANTY/DISCLAIMER Temperature