Omega OME-A822PG manual 9 A/D Software Trigger Control Register

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The software driver provides three data transfer methods, polling, interrupt and DMA. The polling subroutine, A-822_AD_PollingVar() or A-822_AD_PollingArray(), set the A/D mode control register to 0x01. This control word enables software trigger and polling transfer. The interrupt subroutine, A-822_AD_INT_START(…), sets the A/D mode control mode register to ox06. This control word enables pacer trigger and interrupt transfer. The DMA subroutine, A-822_AD_DMA_START(…), sets the A/D mode control register to 0x02. This control word means pacer trigger and DMA transfer.

Please refer to sec. 2.7 for detailed information.

2.4.9A/D Software Trigger Control Register

(WRITE)	Base+C : A/D Software Trigger Control Register
Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
X	X	X	X	X	X	X	X

X=don‘t care, XXXXXXXX=any 8 bits data is validate

The A/D converter can be triggered by software trigger or pacer trigger. The details are given in sec. 2.4.8 and sec. 2.7. Writing any value to address BASE+C will generate a trigger pulse to the A/D converter and initiate an A/D conversion. The address BASE+5 offers a ready bit to indicate an A/D conversion is completed.

The software driver uses this control word to detect the OME-A-822PGL/PGH hardware board. The software initiates a software trigger and checks the ready bit . If the ready bit can not cleared to zero in a fixed time, the software driver will return a error message. If there is an I/O BASE address error, the ready bit will not be cleared to zero. The software driver, A-822_CheckAddress(), uses this method to detect the I/O BASE address setting

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Contents User’sGuide Mexico CanadaBenelux Czech RepublicOME-A-822PGH/PGL Introduction Tables of ContentsConnector General Description FeaturesPower Consumption SpecificationsAnalog Inputs 3 A/D ConverterDigital I/O DA ConverterInterrupt Channel Direct Memory Access Channel DMA Programmable Timer/CounterProduct Check List ApplicationsBoard Layout Hardware ConfigurationDefault base address is I/O Base Address Setting1 JP1 D/A Internal Reference Voltage Selection Jumper Settings3 JP3 Single-ended/Differential Selection 2 JP2 D/A Int/Ext Ref Voltage Selection5 JP5 Interrupt Level Selection 4 JP4 A/D Trigger Source Selection6 JP6 User Timer/Counter Clock Input Selection DRQ JP7 Dack JP8 DMA 7 JP7 DMA Dack Selection JP8 DMA DRQ SelectionAddress Read Write I/O Register Address2 A/D Input Buffer Register 1 8254 CounterConversion is completed, the Ready bit will clear to zero 3 D/A Output Latch Register Clear Interrupt Request 4 D/I Input Buffer RegisterGAIN3 GAIN2 GAIN1 GAIN0 6 A/D Gain Control Register7 A/D Multiplex Control Register OME-A-822PGH Gain Control Code Table8 A/D Mode Control Register 9 A/D Software Trigger Control Register 10 D/O Output Latch Register CN2 Digital I/OCounter 8254 Timer/CounterA/D Conversion Polling, interrupt and DMA 1 A/D conversion flow3 A/D Transfer Modes 2 A/D Conversion Trigger ModesDelay the settling time refer to Sec .4.6 and Sec Using software trigger and polling transferRefer to Sec D/A Conversion Analog Input Signal Connection OME-A-822PGL/PGH Hardware Manual OME-A-822PGL/PGH Hardware Manual Use a single connection to frame ground not A.GND or D.GND Signal ShieldingUsing OME-DB-8225 CJC Output CN1 Digital Input Pin Assignment CN1/CN2/CN3 Pin AssignmentCN2 Digital Output Pin Assignment SINGLE-ENDED Signal Mode Differential Signals OME-DB-8225 Daughter BoardOME-DB-37 OME-DB-16PDescription of Variable Resistors CalibrationD/A Calibration A/D Calibration Introduction Diagnostic UtilityOME-A-822PGL/PGH Hardware Manual Running The Diagnostic Utility Base address selection screen SetupDMA no and IRQ no selection screen Calibration Function Test Test Test Screen Digital I/O Test Screen Multiplexer Test Screen Use IRQ Test Screen Use DMA Test Screen DA Gain Test Screen Timer 0 Test Screen Special Test Help WARRANTY/DISCLAIMER Temperature