Omega OME-A822PG manual 8 A/D Mode Control Register

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2.4.8A/D Mode Control Register

(WRITE)

Base+B : A/D Mode Control Register Format

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

X

X

X

X

X

D2

D1

D0

X=don‘t care

JP4 Select Internal Trigger

Mode Select

Trigger Type

Transfer Type

D2

D1

D0

Software Trig

Pacer Trig

Software

Interrupt

DMA

0

0

0

X

X

X

X

X

0

0

1

Select

X

Select

X

X

0

1

0

X

Select

X

X

Select

1

1

0

X

Select

Select

Select

X

X=disable

JP4 Select External Trigger

Mode Select

Trigger Type

Transfer Type

D2

D1

D0

External Trigger

Software

Interrupt

DMA

0

0

0

X

X

X

X

0

0

1

X

X

X

X

0

1

0

Select

X

X

Select

1

1

0

Select

Select

Select

X

The A/D conversion can be divided into 2 stages, trigger stage and transfer stage. The trigger stage will generate a trigger signal to the A/D converter and the transfer stage will transfer the result to the CPU.

The trigger method may be internal trigger or external trigger. The internal trigger can be software trigger or pacer trigger. The software trigger is simple to use but does not

control the sampling rate very precisely. In the software trigger mode, the program issues a software trigger command (sec 2.4.9) to initiate the A/D conversion. The program then must poll the A/D status bit until the ready bit is 0(sec 2.4.2).

The pacer trigger can control the sample rate very precisely. In the pacer trigger mode, the pacer timer (sec 2.6) will generate periodic trigger signals to the A/D converter. The converted data can be transferred to the CPU by polling or interrupt or by DMA transfer.

OME-A-822PGL/PGH Hardware Manual ---- 22

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Contents User’sGuide Canada MexicoBenelux Czech RepublicOME-A-822PGH/PGL Tables of Contents IntroductionConnector Features General DescriptionSpecifications Power ConsumptionAnalog Inputs 3 A/D ConverterDA Converter Digital I/OInterrupt Channel Programmable Timer/Counter Direct Memory Access Channel DMAApplications Product Check ListHardware Configuration Board LayoutI/O Base Address Setting Default base address isJumper Settings 1 JP1 D/A Internal Reference Voltage Selection2 JP2 D/A Int/Ext Ref Voltage Selection 3 JP3 Single-ended/Differential Selection4 JP4 A/D Trigger Source Selection 5 JP5 Interrupt Level Selection6 JP6 User Timer/Counter Clock Input Selection 7 JP7 DMA Dack Selection JP8 DMA DRQ Selection DRQ JP7 Dack JP8 DMAI/O Register Address Address Read Write1 8254 Counter 2 A/D Input Buffer RegisterConversion is completed, the Ready bit will clear to zero 3 D/A Output Latch Register 4 D/I Input Buffer Register Clear Interrupt Request6 A/D Gain Control Register GAIN3 GAIN2 GAIN1 GAIN0OME-A-822PGH Gain Control Code Table 7 A/D Multiplex Control Register8 A/D Mode Control Register 9 A/D Software Trigger Control Register 10 D/O Output Latch Register Digital I/O CN28254 Timer/Counter CounterA/D Conversion 1 A/D conversion flow Polling, interrupt and DMA2 A/D Conversion Trigger Modes 3 A/D Transfer ModesUsing software trigger and polling transfer Delay the settling time refer to Sec .4.6 and SecRefer to Sec D/A Conversion Analog Input Signal Connection OME-A-822PGL/PGH Hardware Manual OME-A-822PGL/PGH Hardware Manual Signal Shielding Use a single connection to frame ground not A.GND or D.GNDUsing OME-DB-8225 CJC Output CN1/CN2/CN3 Pin Assignment CN1 Digital Input Pin AssignmentCN2 Digital Output Pin Assignment SINGLE-ENDED Signal Mode Differential Signals Daughter Board OME-DB-8225OME-DB-37 OME-DB-16PCalibration Description of Variable ResistorsD/A Calibration A/D Calibration Diagnostic Utility IntroductionOME-A-822PGL/PGH Hardware Manual Running The Diagnostic Utility Setup Base address selection screenDMA no and IRQ no selection screen Calibration Function Test Test Test Screen Digital I/O Test Screen Multiplexer Test Screen Use IRQ Test Screen Use DMA Test Screen DA Gain Test Screen Timer 0 Test Screen Special Test Help WARRANTY/DISCLAIMER Temperature