Cypress 37000 CPLD 0V Device Characteristics Maximum Ratings, Operating Range2, Output Condition

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Ultra37000 CPLD Family

5.0V Device Characteristics

Maximum Ratings

(Above which the useful life may be impaired. For user guide- lines, not tested.)

Storage Temperature

–65°C to +150°C

Ambient Temperature with

 

Power Applied

–55°C to +125°C

Supply Voltage to Ground Potential

–0.5V to +7.0V

DC Voltage Applied to Outputs

 

in High-Z State

–0.5V to +7.0V

DC Input Voltage

–0.5V to +7.0V

DC Program Voltage

4.5 to 5.5V

Current into Outputs

16 mA

Static Discharge Voltage

> 2001V

(per MIL-STD-883, Method 3015)

 

Latch-up Current

> 200 mA

Operating Range[2]

Range

Ambient Temperature[2]

Junction Temperature

Output Condition

V

V

CCO

 

 

 

 

CC

 

Commercial

0°C to +70°C

0°C to +90°C

5V

5V ± 0.25V

5V ± 0.25V

 

 

 

 

 

 

 

 

 

 

3.3V

5V ± 0.25V

3.3V

± 0.3V

 

 

 

 

 

 

Industrial

–40°C to +85°C

–40°C to +105°C

5V

5V ± 0.5V

5V ± 0.5V

 

 

 

 

 

 

 

 

 

 

3.3V

5V ± 0.5V

3.3V

± 0.3V

 

 

 

 

 

 

Military[3]

–55°C to +125°C

–55°C to +130°C

5V

5V ± 0.5V

5V ± 0.5V

 

 

 

3.3V

5V ± 0.5V

3.3V

± 0.3V

 

 

 

 

 

 

 

5.0V Device Electrical Characteristics Over the Operating Range

Parameter

Description

Test Conditions

Min.

Typ.

Max.

Unit

VOH

Output HIGH Voltage

VCC = Min.

IOH = –3.2 mA (Com’l/Ind)[4]

2.4

 

 

V

 

 

 

IOH = –2.0 mA (Mil)[4]

2.4

 

 

V

VOHZ

Output HIGH Voltage with

VCC = Max.

IOH = 0 A (Com’l)[6]

 

 

4.2

V

 

Output Disabled[5]

 

 

 

 

 

 

 

 

IOH = 0 A (Ind/Mil)[6]

 

 

4.5

V

 

 

 

IOH = –100 A (Com’l)[6]

 

 

3.6

V

 

 

 

IOH = –150 A (Ind/Mil)[6]

 

 

3.6

V

VOL

Output LOW Voltage

VCC = Min.

IOL = 16 mA (Com’l/Ind)[4]

 

 

0.5

V

 

 

 

IOL = 12 mA (Mil)[4]

 

 

0.5

V

VIH

Input HIGH Voltage

Guaranteed Input Logical HIGH Voltage for all Inputs[7]

2.0

 

VCCmax

V

VIL

Input LOW Voltage

Guaranteed Input Logical LOW Voltage for all Inputs[7]

–0.5

 

0.8

V

IIX

Input Load Current

VI = GND OR VCC, Bus-Hold Disabled

–10

 

10

A

IOZ

Output Leakage Current

VO = GND or VCC, Output Disabled, Bus-Hold Disabled

–50

 

50

A

IOS

Output Short Circuit Current[5, 8]

VCC = Max., VOUT = 0.5V

 

–30

 

–160

mA

IBHL

Input Bus-Hold LOW

VCC = Min., VIL = 0.8V

 

+75

 

 

A

 

Sustaining Current

 

 

 

 

 

 

IBHH

Input Bus-Hold HIGH

VCC = Min., VIH = 2.0V

 

–75

 

 

A

 

Sustaining Current

 

 

 

 

 

 

IBHLO

Input Bus-Hold LOW

VCC = Max.

 

 

 

+500

A

 

Overdrive Current

 

 

 

 

 

 

IBHHO

Input Bus-Hold HIGH

VCC = Max.

 

 

 

–500

A

 

Overdrive Current

 

 

 

 

 

 

Notes:

 

 

 

 

 

 

 

2.Normal Programming Conditions apply across Ambient Temperature Range for specified programming methods. For more information on programming the Ultra37000 Family devices, please refer to the Application Note titled “An Introduction to In System Reprogramming with the Ultra37000.”

3.TA is the “Instant On” case temperature.

4.IOH = –2 mA, IOL = 2 mA for TDO.

5.Tested initially and after any design or process changes that may affect these parameters.

6.When the I/O is output disabled, the bus-hold circuit can weakly pull the I/O to above 3.6V if no leakage current is allowed. Note that all I/Os are output disabled during ISR programming. Refer to the application note “Understanding Bus-Hold” for additional information.

7.These are absolute values with respect to device ground. All overshoots due to system or tester noise are included.

8.Not more than one output should be tested at a time. Duration of the short circuit should not exceed 1 second. VOUT = 0.5V has been chosen to avoid test problems caused by tester ground degradation.

Document #: 38-03007 Rev. *E

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Contents Ultra37000V 3.3V Devices FeaturesUltra37000 5.0V Devices Cypress Semiconductor CorporationSelection Guide Logic Block Architecture Overview of Ultra37000 FamilyProgrammable Interconnect Matrix Product Term Allocator Ultra37000 MacrocellO and Buried Macrocells Input Macrocell Timing ModelDevelopment Software Support Jtag and PCI StandardsThird-Party Programmers CY37064/CY37064VInput Logic Block DiagramsCY37032/CY37032V CY37128/CY37128V CY37192/CY37192VLogic Block Diagrams CY37256/CY37256VCY37384/CY37384V TMSCY37512/CY37512V Range 0V Device Characteristics Maximum RatingsOperating Range2 Output ConditionInductance5 Endurance Characteristics53V Device Characteristics Maximum Ratings Capacitance5AC Characteristics Switching Characteristics Over the Operating Range Parameter Description Unit Product Term Clocking Parameters Pipelined Mode ParametersReset/Preset Parameters User Option ParametersProduct Term Reset/PresetSynchronous Operating Frequency ParametersJtag Timing Switching WaveformsUser Option Combinatorial OutputLatched Output Latched Input Registered InputClock to Clock Output Enable/Disable Asynchronous ResetAsynchronous Preset Latched Input and OutputCY37064 Power ConsumptionTypical 5.0V Power Consumption CY37032 Typical 5.0V Power Consumption CY37128 CY37192Typical 5.0V Power Consumption CY37256 CY37384Typical 5.0V Power Consumption CY37512 Typical 3.3V Power Consumption CY37032VTypical 3.3V Power Consumption CY37064V CY37128VTypical 3.3V Power Consumption CY37192V CY37256VTypical 3.3V Power Consumption CY37384V CY37512VPin Plcc J67 / Clcc Y67 Top View Pin Configurations20Pin Tqfp A44 Top View Ball Fine-Pitch BGA BA50 Top View Lead Plcc J83 / Clcc Y84 Top ViewLead Tqfp A100 Top View Ball Fine-Pitch BGA BB100 for CY37064V Top View Ball Fine-Pitch BGA BB100 for CY37128V Top ViewCLK3/I4 GND Lead Tqfp A160 for CY37192V Top View TDO I/OLead Pqfp N208 / Cqfp U208 Top View I/O I/O I/O I/O I/O I/O I/O I/OBall Pbga BG292 Top View Ball Fine-Pitch BGA BB256 Top View Lead Pbga BG388 Top View Ball Fine-Pitch BGA BB400 Top View Ordering Information 0V Ordering InformationLead Plastic Leaded Chip Carrier CY37064P84-154JC CY37128P84-167JC Lead Plastic Quad Flat Pack CY37256P256-154BGC 3V Ordering Information BB100 Lead Plastic Quad Flat Pack CY37256VP256-100BGC Lead Lead Pb-Free Plastic Leaded Chip Carrier J67 Package DiagramsLead Lead Pb-Free Thin Plastic Quad Flat Pack A44 Lead Ceramic Leaded Chip Carrier Y67 Ball 7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch Thin BGA BA48D Lead Lead Pb-Free Plastic Leaded Chip Carrier J83Lead Ceramic Leaded Chip Carrier Y84 Lead Lead Pb-Free Thin Plastic Quad Flat Pack Tqfp A100 Ball Thin Ball Grid Array 11 x 11 x 1.4 mm BB100 51-85049-*B Lead Ceramic Quad Flatpack Cavity Up U162 Detail aLead Plastic Quad Flatpack N208 Lead Ceramic Quad Flatpack Cavity Up U208 Ball Fbga 17 x 17 mm BB256 Bottom ViewBall Plastic Ball Grid Array Pbga 27 x 27 x 2.33 mm BG292 Ball Plastic Ball Grid Array Pbga 35 x 35 x 2.33 mm BG388 Ball Fbga 21 x 21 x 1.4 mm BB400 3V ± Addendum 3V Operating RangeCommercial Issue Orig. Description of Change Date Document History