Cypress 37000 CPLD manual Parameter Description Unit Product Term Clocking Parameters

Page 18

Ultra37000 CPLD Family

Switching Characteristics Over the Operating Range (continued)[12]

Parameter

Description

Unit

Product Term Clocking Parameters

tCOPT[13, 14, 15]

Product Term Clock or Latch Enable (PTCLK) to Output

ns

tSPT

Set-Up Time from Input to Product Term Clock or Latch Enable (PTCLK)

ns

tHPT

Register or Latch Data Hold Time

ns

tISPT[13]

Set-Up Time for Buried Register used as an Input Register from Input to Product Term Clock or

ns

Latch Enable (PTCLK)

tIHPT

Buried Register Used as an Input Register or Latch Data Hold Time

ns

tCO2PT[13, 14, 15]

Product Term Clock or Latch Enable (PTCLK) to Output Delay (Through Logic Array)

ns

Pipelined Mode Parameters

tICS[13]

Input Register Synchronous Clock (CLK0, CLK1, CLK2, or CLK3) to Output Register Synchronous

ns

Clock (CLK0, CLK1, CLK2, or CLK3)

Operating Frequency

Parameters

f

MAX1

Maximum Frequency with Internal Feedback (Lesser of 1/t , 1/(t

+ t ), or 1/t

)[5]

MHz

SCS

S

H

CO

fMAX2

Maximum Frequency Data Path in Output Registered/Latched Mode (Lesser of 1/(tWL + tWH),

MHz

1/(t

S

+ t

), or 1/t

)[5]

H

CO

f

MAX3

Maximum Frequency with External Feedback (Lesser of 1/(t

CO

+ t

S

) or 1/(t

WL

+ t

)[5]

MHz

WH

fMAX4

Maximum Frequency in Pipelined Mode (Lesser of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH),

MHz

or 1/tSCS)[5]

Reset/Preset Parameters

t

RW

Asynchronous Reset Width[5]

ns

t

[13]

Asynchronous Reset Recovery Time[5]

ns

RR

tRO[13, 14, 15]

Asynchronous Reset to Output

ns

tPW

Asynchronous Preset Width[5]

ns

tPR[13]

Asynchronous Preset Recovery Time[5]

ns

tPO[13, 14, 15]

Asynchronous Preset to Output

ns

User Option Parameters

tLP

Low Power Adder

ns

tSLEW

Slow Output Slew Rate Adder

ns

t3.3IO

3.3V I/O Mode Timing Adder[5]

ns

JTAG Timing Parameters

t

S JTAG

Set-up Time from TDI and TMS to TCK[5]

ns

tH JTAG

Hold Time on TDI and TMS[5]

ns

tCO JTAG

Falling Edge of TCK to TDO[5]

ns

f

JTAG

Maximum JTAG Tap Controller Frequency[5]

ns

Document #: 38-03007 Rev. *E

Page 18 of 64

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Contents Ultra37000V 3.3V Devices FeaturesUltra37000 5.0V Devices Cypress Semiconductor CorporationSelection Guide Architecture Overview of Ultra37000 Family Programmable Interconnect MatrixLogic Block Product Term Allocator Ultra37000 MacrocellO and Buried Macrocells Input Macrocell Timing ModelDevelopment Software Support Jtag and PCI StandardsThird-Party Programmers Logic Block Diagrams CY37032/CY37032VCY37064/CY37064VInput CY37128/CY37128V CY37192/CY37192VLogic Block Diagrams CY37256/CY37256VCY37384/CY37384V TMSCY37512/CY37512V Range 0V Device Characteristics Maximum RatingsOperating Range2 Output ConditionInductance5 Endurance Characteristics53V Device Characteristics Maximum Ratings Capacitance5AC Characteristics Switching Characteristics Over the Operating Range Parameter Description Unit Product Term Clocking Parameters Pipelined Mode ParametersReset/Preset Parameters User Option ParametersProduct Term Reset/PresetSynchronous Operating Frequency ParametersJtag Timing Switching WaveformsUser Option Combinatorial OutputLatched Output Registered Input Clock to ClockLatched Input Output Enable/Disable Asynchronous ResetAsynchronous Preset Latched Input and OutputPower Consumption Typical 5.0V Power Consumption CY37032CY37064 Typical 5.0V Power Consumption CY37128 CY37192Typical 5.0V Power Consumption CY37256 CY37384Typical 5.0V Power Consumption CY37512 Typical 3.3V Power Consumption CY37032VTypical 3.3V Power Consumption CY37064V CY37128VTypical 3.3V Power Consumption CY37192V CY37256VTypical 3.3V Power Consumption CY37384V CY37512VPin Configurations20 Pin Tqfp A44 Top ViewPin Plcc J67 / Clcc Y67 Top View Ball Fine-Pitch BGA BA50 Top View Lead Plcc J83 / Clcc Y84 Top ViewLead Tqfp A100 Top View Ball Fine-Pitch BGA BB100 for CY37064V Top View Ball Fine-Pitch BGA BB100 for CY37128V Top ViewCLK3/I4 GND Lead Tqfp A160 for CY37192V Top View TDO I/OLead Pqfp N208 / Cqfp U208 Top View I/O I/O I/O I/O I/O I/O I/O I/OBall Pbga BG292 Top View Ball Fine-Pitch BGA BB256 Top View Lead Pbga BG388 Top View Ball Fine-Pitch BGA BB400 Top View Ordering Information 0V Ordering InformationLead Plastic Leaded Chip Carrier CY37064P84-154JC CY37128P84-167JC Lead Plastic Quad Flat Pack CY37256P256-154BGC 3V Ordering Information BB100 Lead Plastic Quad Flat Pack CY37256VP256-100BGC Package Diagrams Lead Lead Pb-Free Thin Plastic Quad Flat Pack A44Lead Lead Pb-Free Plastic Leaded Chip Carrier J67 Lead Ceramic Leaded Chip Carrier Y67 Ball 7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch Thin BGA BA48D Lead Lead Pb-Free Plastic Leaded Chip Carrier J83Lead Ceramic Leaded Chip Carrier Y84 Lead Lead Pb-Free Thin Plastic Quad Flat Pack Tqfp A100 Ball Thin Ball Grid Array 11 x 11 x 1.4 mm BB100 51-85049-*B Lead Ceramic Quad Flatpack Cavity Up U162 Detail aLead Plastic Quad Flatpack N208 Lead Ceramic Quad Flatpack Cavity Up U208 Ball Fbga 17 x 17 mm BB256 Bottom ViewBall Plastic Ball Grid Array Pbga 27 x 27 x 2.33 mm BG292 Ball Plastic Ball Grid Array Pbga 35 x 35 x 2.33 mm BG388 Ball Fbga 21 x 21 x 1.4 mm BB400 Addendum 3V Operating Range Commercial3V ± Issue Orig. Description of Change Date Document History