Cypress 37000 CPLD manual Ball Fbga 17 x 17 mm BB256, Bottom View

Page 59

Ultra37000 CPLD Family

Package Diagrams (continued)

256-Ball FBGA (17 x 17 mm) BB256

TOP VIEW

PIN 1 CORNER

BOTTOM VIEW

		Ø0.05 M C

		Ø0.25 M C A B
				PIN 1 CORNER
Ø0.45±0.05(256X)-CPLD DEVICES (37K & 39K)
+0.10
Ø0.50 (256X)-ALL OTHER DEVICES
-0.05

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

17.00±0.10

B

1.00

15.00

7.50

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

1.00

0.25 C

0.70±0.05

A1

SEATING PLANE

C

A1	0.36	0.56

A	1.40 MAX. 1.70 MAX.

0.15 C

A

+0.10 0.35 -0.05

7.50

15.00

A	17.00±0.10

0.20(4X)

REFERENCE JEDEC MO-192

51-85108-*F

Document #: 38-03007 Rev. *E

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Contents Cypress Semiconductor Corporation FeaturesUltra37000 5.0V Devices Ultra37000V 3.3V DevicesSelection Guide Logic Block Architecture Overview of Ultra37000 FamilyProgrammable Interconnect Matrix Ultra37000 Macrocell Product Term AllocatorO and Buried Macrocells Timing Model Input MacrocellJtag and PCI Standards Development Software SupportThird-Party Programmers CY37064/CY37064VInput Logic Block DiagramsCY37032/CY37032V CY37192/CY37192V CY37128/CY37128VCY37256/CY37256V Logic Block DiagramsTMS CY37384/CY37384VCY37512/CY37512V Output Condition 0V Device Characteristics Maximum RatingsOperating Range2 RangeCapacitance5 Endurance Characteristics53V Device Characteristics Maximum Ratings Inductance5AC Characteristics Switching Characteristics Over the Operating Range User Option Parameters Pipelined Mode ParametersReset/Preset Parameters Parameter Description Unit Product Term Clocking ParametersOperating Frequency Parameters Reset/PresetSynchronous Product TermCombinatorial Output Switching WaveformsUser Option Jtag TimingLatched Output Latched Input Registered InputClock to Clock Latched Input and Output Asynchronous ResetAsynchronous Preset Output Enable/DisableCY37064 Power ConsumptionTypical 5.0V Power Consumption CY37032 CY37192 Typical 5.0V Power Consumption CY37128CY37384 Typical 5.0V Power Consumption CY37256Typical 3.3V Power Consumption CY37032V Typical 5.0V Power Consumption CY37512CY37128V Typical 3.3V Power Consumption CY37064VCY37256V Typical 3.3V Power Consumption CY37192VCY37512V Typical 3.3V Power Consumption CY37384VPin Plcc J67 / Clcc Y67 Top View Pin Configurations20Pin Tqfp A44 Top View Lead Plcc J83 / Clcc Y84 Top View Ball Fine-Pitch BGA BA50 Top ViewLead Tqfp A100 Top View Ball Fine-Pitch BGA BB100 for CY37128V Top View Ball Fine-Pitch BGA BB100 for CY37064V Top ViewCLK3/I4 GND TDO I/O Lead Tqfp A160 for CY37192V Top ViewI/O I/O I/O I/O I/O I/O I/O I/O Lead Pqfp N208 / Cqfp U208 Top ViewBall Pbga BG292 Top View Ball Fine-Pitch BGA BB256 Top View Lead Pbga BG388 Top View Ball Fine-Pitch BGA BB400 Top View 0V Ordering Information Ordering InformationLead Plastic Leaded Chip Carrier CY37064P84-154JC CY37128P84-167JC Lead Plastic Quad Flat Pack CY37256P256-154BGC 3V Ordering Information BB100 Lead Plastic Quad Flat Pack CY37256VP256-100BGC Lead Lead Pb-Free Plastic Leaded Chip Carrier J67 Package DiagramsLead Lead Pb-Free Thin Plastic Quad Flat Pack A44 Lead Ceramic Leaded Chip Carrier Y67 Lead Lead Pb-Free Plastic Leaded Chip Carrier J83 Ball 7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch Thin BGA BA48DLead Ceramic Leaded Chip Carrier Y84 Lead Lead Pb-Free Thin Plastic Quad Flat Pack Tqfp A100 Ball Thin Ball Grid Array 11 x 11 x 1.4 mm BB100 51-85049-*B Detail a Lead Ceramic Quad Flatpack Cavity Up U162Lead Plastic Quad Flatpack N208 Lead Ceramic Quad Flatpack Cavity Up U208 Bottom View Ball Fbga 17 x 17 mm BB256Ball Plastic Ball Grid Array Pbga 27 x 27 x 2.33 mm BG292 Ball Plastic Ball Grid Array Pbga 35 x 35 x 2.33 mm BG388 Ball Fbga 21 x 21 x 1.4 mm BB400 3V ± Addendum 3V Operating RangeCommercial Document History Issue Orig. Description of Change Date