Cypress 37000 CPLD manual Logic Block Diagrams, CY37032/CY37032V, CY37064/CY37064VInput

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Ultra37000 CPLD Family

Logic Block Diagrams

CY37032/CY37032V					Clock/
				Input	Input		TDI	JTAG Tap
							TDI
							TCK
				1	4		TCK	Controller
				1	4		TMS	Controller
		4				4		JTAGEN
		4	36		36	4
	16 I/Os	LOGIC	36		36	LOGIC		16 I/Os
	16 I/Os	LOGIC		PIM		LOGIC		16 I/Os
I/O	−I/O	BLOCK	16	PIM	16	BLOCK		I/O16−I/O31
0	15	A				B
		16				16

TDO

Clock/

CY37064/CY37064VInput

Input

16 I/Os

I/O0-I/O15

16 I/Os

I/O16-I/O31

TDI

JTAG Tap

TCK

Controller

TMS

		1	4
4				4
	36		36
LOGIC				LOGIC	16 I/Os
BLOCK	16		16	BLOCK	I/O48-I/O63
A		PIM		D
	36	PIM	36		16 I/Os
LOGIC	36			LOGIC
LOGIC				LOGIC
BLOCK	16		16	BLOCK	I/O32-I/O47
B				C
32				32
TDO

Document #: 38-03007 Rev. *E

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Contents Ultra37000 5.0V Devices FeaturesUltra37000V 3.3V Devices Cypress Semiconductor CorporationSelection Guide Architecture Overview of Ultra37000 Family Programmable Interconnect MatrixLogic Block Ultra37000 Macrocell Product Term AllocatorO and Buried Macrocells Timing Model Input MacrocellJtag and PCI Standards Development Software SupportThird-Party Programmers Logic Block Diagrams CY37032/CY37032VCY37064/CY37064VInput CY37192/CY37192V CY37128/CY37128VCY37256/CY37256V Logic Block DiagramsTMS CY37384/CY37384VCY37512/CY37512V Operating Range2 0V Device Characteristics Maximum RatingsRange Output Condition3V Device Characteristics Maximum Ratings Endurance Characteristics5Inductance5 Capacitance5AC Characteristics Switching Characteristics Over the Operating Range Reset/Preset Parameters Pipelined Mode ParametersParameter Description Unit Product Term Clocking Parameters User Option ParametersSynchronous Reset/PresetProduct Term Operating Frequency ParametersUser Option Switching WaveformsJtag Timing Combinatorial OutputLatched Output Registered Input Clock to ClockLatched Input Asynchronous Preset Asynchronous ResetOutput Enable/Disable Latched Input and OutputPower Consumption Typical 5.0V Power Consumption CY37032CY37064 CY37192 Typical 5.0V Power Consumption CY37128CY37384 Typical 5.0V Power Consumption CY37256Typical 3.3V Power Consumption CY37032V Typical 5.0V Power Consumption CY37512CY37128V Typical 3.3V Power Consumption CY37064VCY37256V Typical 3.3V Power Consumption CY37192VCY37512V Typical 3.3V Power Consumption CY37384VPin Configurations20 Pin Tqfp A44 Top ViewPin Plcc J67 / Clcc Y67 Top View Lead Plcc J83 / Clcc Y84 Top View Ball Fine-Pitch BGA BA50 Top ViewLead Tqfp A100 Top View Ball Fine-Pitch BGA BB100 for CY37128V Top View Ball Fine-Pitch BGA BB100 for CY37064V Top ViewCLK3/I4 GND TDO I/O Lead Tqfp A160 for CY37192V Top ViewI/O I/O I/O I/O I/O I/O I/O I/O Lead Pqfp N208 / Cqfp U208 Top ViewBall Pbga BG292 Top View Ball Fine-Pitch BGA BB256 Top View Lead Pbga BG388 Top View Ball Fine-Pitch BGA BB400 Top View 0V Ordering Information Ordering InformationLead Plastic Leaded Chip Carrier CY37064P84-154JC CY37128P84-167JC Lead Plastic Quad Flat Pack CY37256P256-154BGC 3V Ordering Information BB100 Lead Plastic Quad Flat Pack CY37256VP256-100BGC Package Diagrams Lead Lead Pb-Free Thin Plastic Quad Flat Pack A44Lead Lead Pb-Free Plastic Leaded Chip Carrier J67 Lead Ceramic Leaded Chip Carrier Y67 Lead Lead Pb-Free Plastic Leaded Chip Carrier J83 Ball 7.0 mm x 7.0 mm x 1.2 mm, 0.80 pitch Thin BGA BA48DLead Ceramic Leaded Chip Carrier Y84 Lead Lead Pb-Free Thin Plastic Quad Flat Pack Tqfp A100 Ball Thin Ball Grid Array 11 x 11 x 1.4 mm BB100 51-85049-*B Detail a Lead Ceramic Quad Flatpack Cavity Up U162Lead Plastic Quad Flatpack N208 Lead Ceramic Quad Flatpack Cavity Up U208 Bottom View Ball Fbga 17 x 17 mm BB256Ball Plastic Ball Grid Array Pbga 27 x 27 x 2.33 mm BG292 Ball Plastic Ball Grid Array Pbga 35 x 35 x 2.33 mm BG388 Ball Fbga 21 x 21 x 1.4 mm BB400 Addendum 3V Operating Range Commercial3V ± Document History Issue Orig. Description of Change Date